[PATCH] drm/amdgpu: Release SDMAv4.4.2 ecc irq properly

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar at amd.com>
Sent: Tuesday, June 13, 2023 18:46
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Kamal, Asad <Asad.Kamal at amd.com>; Ma, Le <Le.Ma at amd.com>
Subject: [PATCH] drm/amdgpu: Release SDMAv4.4.2 ecc irq properly

Release ECC irq only if irq is enabled - only when RAS feature is enabled ECC irq gets enabled.

Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 8eebf9c2bbcd..77ebf27981e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1434,9 +1434,11 @@ static int sdma_v4_4_2_hw_fini(void *handle)
                return 0;

        inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
-       for (i = 0; i < adev->sdma.num_instances; i++) {
-               amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
-                              AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+               }
        }

        sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); @@ -2073,9 +2075,12 @@ static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
        uint32_t tmp_mask = inst_mask;
        int i;

-       for_each_inst(i, tmp_mask) {
-               amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
-                              AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+               for_each_inst(i, tmp_mask)
+               {
+                       amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+               }
        }

        sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
--
2.25.1