[PATCH] drm/amdgpu: Clear VCN cache when hw_init

[Deng, Emily]

[AMD Official Use Only - General]

Reviewed-by: Emily Deng <Emily.Deng at amd.com>

>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Horace
>Chen
>Sent: Tuesday, June 20, 2023 9:30 PM
>To: amd-gfx at lists.freedesktop.org
>Cc: Andrey Grodzovsky <Andrey.Grodzovsky at amd.com>; Xiao, Jack
><Jack.Xiao at amd.com>; Xu, Feifei <Feifei.Xu at amd.com>; Chen, Horace
><Horace.Chen at amd.com>; Chang, HaiJun <HaiJun.Chang at amd.com>;
>Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan
><Evan.Quan at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Liu,
>Monk <Monk.Liu at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>
>Subject: [PATCH] drm/amdgpu: Clear VCN cache when hw_init
>
>[Why]
>VCN will use some framebuffer space as its cache. It needs to be reset when
>reset happens, such as FLR. Otherwise some error may be kept after the reset.
>
>Signed-off-by: Horace Chen <horace.chen at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>index b48bb5212488..2db73a964031 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>@@ -1292,6 +1292,7 @@ static int vcn_v4_0_start_sriov(struct
>amdgpu_device *adev)
>                       cache_size);
>
>               cache_addr = adev->vcn.inst[i].gpu_addr + offset;
>+              memset(adev->vcn.inst[i].cpu_addr + offset, 0,
>+AMDGPU_VCN_STACK_SIZE);
>
>       MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>                       regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>                       lower_32_bits(cache_addr));
>@@ -1307,6 +1308,8 @@ static int vcn_v4_0_start_sriov(struct
>amdgpu_device *adev)
>
>               cache_addr = adev->vcn.inst[i].gpu_addr + offset +
>                       AMDGPU_VCN_STACK_SIZE;
>+              memset(adev->vcn.inst[i].cpu_addr + offset +
>AMDGPU_VCN_STACK_SIZE, 0,
>+                      AMDGPU_VCN_STACK_SIZE);
>
>       MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>                       regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>                       lower_32_bits(cache_addr));
>--
>2.34.1