[PATCH] Revert "drm/amdgpu: Enable VM_CONTEXT1_CNTL after page table addr is set."
Christian König
ckoenig.leichtzumerken at gmail.com
Mon Jun 26 13:17:02 UTC 2023
Am 31.05.23 um 16:39 schrieb Alex Deucher:
> This reverts commit f57a74f5b42d1627bd5366f88952d42819e91146.
>
> After talking this over with Christian, the original programming
> sequence was correct. The enable bit needs to be set before
> programming the rest of the context.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> Cc: Zibin Liu <ghostfly23333 at gmail.com>
Sorry for the delay, I'm only catching up to mails from lost month by now.
Reviewed-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 6 +-----
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 7 +------
> 15 files changed, 15 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 52a1e79ee4d8..d94cc1ec7242 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -261,7 +261,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> @@ -302,9 +302,6 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> index 108674f6eef0..4dabf910334b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> @@ -330,7 +330,7 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
> hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> @@ -377,9 +377,6 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
> regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
> }
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> index 502cb6e1fe84..f173a61c6c15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> @@ -288,7 +288,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
> @@ -324,9 +324,6 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index c5dbd5af23f0..d8fc3e8088cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -297,7 +297,7 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
> @@ -333,9 +333,6 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
> index d7f86a6834a1..c53147f9c9fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
> @@ -296,7 +296,7 @@ static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
> @@ -332,9 +332,6 @@ static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> index 3371597a7280..ae777487d72e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> @@ -301,7 +301,7 @@ static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
> @@ -337,9 +337,6 @@ static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 22070a379140..fb91b31056ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -243,7 +243,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> @@ -280,9 +280,6 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> index f746981a7d4e..9086f2fdfaf4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
> @@ -275,7 +275,7 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> @@ -314,9 +314,6 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> index 618019caca8e..5e8b493f8699 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> @@ -346,7 +346,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
> tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
> i);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> - ENABLE_CONTEXT, 0);
> + ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> PAGE_TABLE_DEPTH, num_level);
> tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> @@ -388,10 +388,6 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
> regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
> - ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
> }
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index d4b9796389cf..8f76c6ecf50a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -368,7 +368,7 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> @@ -405,9 +405,6 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> index d9d5e698060e..8bd0fc8d9d25 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> @@ -286,7 +286,7 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> @@ -323,9 +323,6 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> index a18b61a39866..441379e91cfa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> @@ -325,7 +325,7 @@ static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> @@ -362,9 +362,6 @@ static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
> index 92e86bc64bcb..12c7f4b46ea9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
> @@ -312,7 +312,7 @@ static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> @@ -349,9 +349,6 @@ static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
> index 0f01ead6d105..5dadc85abf7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
> @@ -317,7 +317,7 @@ static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
>
> for (i = 0; i <= 14; i++) {
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
> + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
> adev->vm_manager.num_level);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> @@ -354,9 +354,6 @@ static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
> - i * hub->ctx_distance, tmp);
> }
>
> hub->vm_cntx_cntl = tmp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> index 18391a0fdf0c..e790f890aec6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
> @@ -310,7 +310,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
> tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
> hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
> tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
> - ENABLE_CONTEXT, 0);
> + ENABLE_CONTEXT, 1);
> tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
> PAGE_TABLE_DEPTH,
> num_level);
> @@ -357,11 +357,6 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
> hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> - tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
> - ENABLE_CONTEXT, 1);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
> - hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
> - i * hub->ctx_distance, tmp);
> }
> }
>
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