[PATCH] drm/amdgpu: Keep non-psp path for partition switch

[Gadre, Mangesh]

[AMD Official Use Only - General]

[AMD Official Use Only - General]

Reviewed-by: Mangesh Gadre <Mangesh.Gadre at amd.com>

Regards,
Mangesh

-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar at amd.com>
Sent: Tuesday, June 27, 2023 10:49 AM
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Gadre, Mangesh <Mangesh.Gadre at amd.com>
Subject: [PATCH] drm/amdgpu: Keep non-psp path for partition switch

When PSP block is not present, use direct programming.

Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
Acked-by: Mangesh Gadre <Mangesh.Gadre at amd.com>
Tested-by: Mangesh Gadre <Mangesh.Gadre at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 +++++++++++++++++++------
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 76b189bd244a..9e3b835bdbb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -623,12 +623,28 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,  static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                int num_xccs_per_xcp)
 {
-       int ret;
-
-       ret = psp_spatial_partition(&adev->psp, NUM_XCC(adev->gfx.xcc_mask) /
-                                                       num_xccs_per_xcp);
-       if (ret)
-               return ret;
+       int ret, i, num_xcc;
+       u32 tmp = 0;
+
+       if (adev->psp.funcs) {
+               ret = psp_spatial_partition(&adev->psp,
+                                           NUM_XCC(adev->gfx.xcc_mask) /
+                                                   num_xccs_per_xcp);
+               if (ret)
+                       return ret;
+       } else {
+               num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+
+               for (i = 0; i < num_xcc; i++) {
+                       tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
+                                           num_xccs_per_xcp);
+                       tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
+                                           i % num_xccs_per_xcp);
+                       WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
+                                    tmp);
+               }
+               ret = 0;
+       }

        adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;

--
2.25.1