[PATCH] drm/amdgpu: Stop clearing kiq position during fini

[Yin, ZhenGuo (Chris)]

Acked-by: ZhenGuo Yin <zhenguo.yin at amd.com>

On 2/27/2023 2:45 PM, Yaoyao Lei wrote:
> Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform
> IDLE-SAVE after VF fini.
> Otherwise it could cause GFX hang if another Win guest is rendering.
>
> Signed-off-by: Yaoyao Lei <yaoyao.lei at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 +++-----------
>   1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 6983acc456b2..073f5f23bc3b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7285,17 +7285,9 @@ static int gfx_v10_0_hw_fini(void *handle)
>   
>   	if (amdgpu_sriov_vf(adev)) {
>   		gfx_v10_0_cp_gfx_enable(adev, false);
> -		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
> -		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> -			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
> -			tmp &= 0xffffff00;
> -			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
> -		} else {
> -			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
> -			tmp &= 0xffffff00;
> -			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
> -		}
> -
> +		/* Remove the steps of clearing KIQ position.
> +		 * It causes GFX hang when another Win guest is rendering.
> +		 */
>   		return 0;
>   	}
>   	gfx_v10_0_cp_enable(adev, false);