[PATCH v3 09/17] drm/amd/display: Register Colorspace property for DP and HDMI

[Ville Syrjälä]

On Thu, Mar 16, 2023 at 01:37:24AM +0100, Sebastian Wick wrote:
> On Tue, Mar 7, 2023 at 4:12 PM Harry Wentland <harry.wentland at amd.com> wrote:
> >
> > We want compositors to be able to set the output
> > colorspace on DP and HDMI outputs, based on the
> > caps reported from the receiver via EDID.
> 
> About that... The documentation says that user space has to check the
> EDID for what the sink actually supports. So whatever is in
> supported_colorspaces is just what the driver/hardware is able to set
> but doesn't actually indicate that the sink supports it.
> 
> So the only way to enable bt2020 is by checking if the sink supports
> both RGB and YUV variants because both could be used by the driver.
> Not great at all. Something to remember for the new property.

Hmm. I wonder if that's even legal... Looks like maybe it
is since I can't immediately spot anything in CTA-861 to
forbid it :/

> 
> > Signed-off-by: Harry Wentland <harry.wentland at amd.com>
> > Cc: Pekka Paalanen <ppaalanen at gmail.com>
> > Cc: Sebastian Wick <sebastian.wick at redhat.com>
> > Cc: Vitaly.Prosyak at amd.com
> > Cc: Joshua Ashton <joshua at froggi.es>
> > Cc: dri-devel at lists.freedesktop.org
> > Cc: amd-gfx at lists.freedesktop.org
> > Reviewed-By: Joshua Ashton <joshua at froggi.es>
> > ---
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index f91b2ea13d96..2d883c6dae90 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -7184,6 +7184,12 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
> >         return amdgpu_dm_connector->num_modes;
> >  }
> >
> > +static const u32 supported_colorspaces =
> > +       BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
> > +       BIT(DRM_MODE_COLORIMETRY_OPRGB) |
> > +       BIT(DRM_MODE_COLORIMETRY_BT2020) |
> > +       BIT(DRM_MODE_COLORIMETRY_BT2020_DEPRECATED);
> > +
> >  void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
> >                                      struct amdgpu_dm_connector *aconnector,
> >                                      int connector_type,
> > @@ -7264,6 +7270,15 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
> >                                 adev->mode_info.abm_level_property, 0);
> >         }
> >
> > +       if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
> > +               if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
> > +                       drm_connector_attach_colorspace_property(&aconnector->base);
> > +       } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > +                  connector_type == DRM_MODE_CONNECTOR_eDP) {
> > +               if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
> > +                       drm_connector_attach_colorspace_property(&aconnector->base);
> > +       }
> > +
> >         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> >             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> >             connector_type == DRM_MODE_CONNECTOR_eDP) {
> > --
> > 2.39.2
> >

-- 
Ville Syrjälä
Intel