[PATCH] drm/amdgpu: enable sysfs node pp_dpm_vclk1 for some asics

[Quan, Evan]

[AMD Official Use Only - General]

IIRC, the VCLK1 always have the same frequency as VCLK0 with our current implementation.
So, is it necessary to provide another sysfs node for checking vclk1 frequency?

BR
Evan
> -----Original Message-----
> From: Tong Liu01 <Tong.Liu01 at amd.com>
> Sent: Tuesday, March 28, 2023 7:42 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan at amd.com>; Chen, Horace
> <Horace.Chen at amd.com>; Tuikov, Luben <Luben.Tuikov at amd.com>;
> Koenig, Christian <Christian.Koenig at amd.com>; Deucher, Alexander
> <Alexander.Deucher at amd.com>; Xiao, Jack <Jack.Xiao at amd.com>; Zhang,
> Hawking <Hawking.Zhang at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Xu,
> Feifei <Feifei.Xu at amd.com>; Wang, Yang(Kevin)
> <KevinYang.Wang at amd.com>; Liu01, Tong (Esther) <Tong.Liu01 at amd.com>
> Subject: [PATCH] drm/amdgpu: enable sysfs node pp_dpm_vclk1 for some
> asics
> 
> Add sysfs node pp_dpm_vclk1 for gc11.0.3
> 
> Signed-off-by: Tong Liu01 <Tong.Liu01 at amd.com>
> ---
>  .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c            | 22
> +++++++++++++++++++
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     |  4 ++++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 86b6b0c9fb02..fe75497eeeab 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -104,6 +104,7 @@ enum pp_clock_type {
>  	PP_FCLK,
>  	PP_DCEFCLK,
>  	PP_VCLK,
> +	PP_VCLK1,
>  	PP_DCLK,
>  	OD_SCLK,
>  	OD_MCLK,
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index d75a67cfe523..1da6e9469450 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -1180,6 +1180,21 @@ static ssize_t amdgpu_set_pp_dpm_vclk(struct
> device *dev,
>  	return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
>  }
> 
> +static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
> +		struct device_attribute *attr,
> +		char *buf)
> +{
> +	return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
> +}
> +
> +static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
> +		struct device_attribute *attr,
> +		const char *buf,
> +		size_t count)
> +{
> +	return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
> +}
> +
>  static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
>  		struct device_attribute *attr,
>  		char *buf)
> @@ -2002,6 +2017,7 @@ static struct amdgpu_device_attr
> amdgpu_device_attrs[] = {
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> +	AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,
> 		ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
>  	AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,
> 	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> @@ -2091,6 +2107,12 @@ static int default_attr_update(struct
> amdgpu_device *adev, struct amdgpu_device_
>  		      gc_ver == IP_VERSION(11, 0, 2) ||
>  		      gc_ver == IP_VERSION(11, 0, 3)))
>  			*states = ATTR_STATE_UNSUPPORTED;
> +	} else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
> +		if (!((gc_ver == IP_VERSION(10, 3, 1) ||
> +		       gc_ver == IP_VERSION(10, 3, 0) ||
> +			   gc_ver == IP_VERSION(11, 0, 2) ||
> +			   gc_ver == IP_VERSION(11, 0, 3)) && adev-
> >vcn.num_vcn_inst >= 2))
> +			*states = ATTR_STATE_UNSUPPORTED;
>  	} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
>  		if (!(gc_ver == IP_VERSION(10, 3, 1) ||
>  		      gc_ver == IP_VERSION(10, 3, 0) ||
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index b5d64749990e..bffbef3f666d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2006,6 +2006,8 @@ static int smu_force_ppclk_levels(void *handle,
>  		clk_type = SMU_DCEFCLK; break;
>  	case PP_VCLK:
>  		clk_type = SMU_VCLK; break;
> +	case PP_VCLK1:
> +		clk_type = SMU_VCLK1; break;
>  	case PP_DCLK:
>  		clk_type = SMU_DCLK; break;
>  	case OD_SCLK:
> @@ -2393,6 +2395,8 @@ static enum smu_clk_type
> smu_convert_to_smuclk(enum pp_clock_type type)
>  		clk_type = SMU_DCEFCLK; break;
>  	case PP_VCLK:
>  		clk_type = SMU_VCLK; break;
> +	case PP_VCLK1:
> +		clk_type = SMU_VCLK1; break;
>  	case PP_DCLK:
>  		clk_type = SMU_DCLK; break;
>  	case OD_SCLK:
> --
> 2.34.1