[PATCH 09/13] drm/amdgpu: add get_gfx_shadow_info callback for gfx11

Alex Deucher alexdeucher at gmail.com
Thu Mar 30 18:48:35 UTC 2023


On Thu, Mar 30, 2023 at 2:16 AM Christian König
<ckoenig.leichtzumerken at gmail.com> wrote:
>
> Am 29.03.23 um 17:25 schrieb Alex Deucher:
> > Used to get the size and alignment requirements for
> > the gfx shadow buffer for preemption.
> >
> > v2: use FW version check to determine whether to
> >      return a valid size here
> >      return an error if not supported (Alex)
> > v3: drop GDS (Alex)
> >
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 25 +++++++++++++++++++++++++
> >   1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > index 1fc1e941f7df..df2eabf50e6e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > @@ -822,6 +822,30 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
> >       soc21_grbm_select(adev, me, pipe, q, vm);
> >   }
> >
> > +/* all sizes are in bytes */
> > +#define MQD_SHADOW_BASE_SIZE      73728
> > +#define MQD_SHADOW_BASE_ALIGNMENT 256
> > +#define MQD_FWWORKAREA_SIZE       484
> > +#define MQD_FWWORKAREA_ALIGNMENT  256
> > +
> > +static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
> > +                                      struct amdgpu_gfx_shadow_info *shadow_info)
> > +{
> > +     if (shadow_info) {
>
> Why would anybody call this without parameter?

They shouldn't.  I'll drop it.

Alex

>
> Christian.
>
> > +             if (adev->gfx.cp_gfx_shadow) {
> > +                     shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
> > +                     shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
> > +                     shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
> > +                     shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
> > +                     return 0;
> > +             } else {
> > +                     memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
> > +                     return -ENOTSUPP;
> > +             }
> > +     }
> > +     return -EINVAL;
> > +}
> > +
> >   static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
> >       .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
> >       .select_se_sh = &gfx_v11_0_select_se_sh,
> > @@ -830,6 +854,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
> >       .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
> >       .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
> >       .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
> > +     .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
> >   };
> >
> >   static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
>


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