[PATCH 20/23] drm/amdgpu: Force GART page table on system memory

[Alex Deucher]

From: Rajneesh Bhardwaj <rajneesh.bhardwaj at amd.com>

[NOT FOR UPSTREAM]

For debug purpose and more test coverage, we want to enable GART in the
system memory for GFXIP9.4.3 bring up branch while we still continue to
use the APU in the carveout mode.

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>
Suggested-by: Harish Kasiviswanathan <Harish.Kasiviswanathan at amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 8 ++++++++
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c  | 2 +-
 5 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c894fb43786c..a0d05a7a29f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -246,6 +246,8 @@ extern int amdgpu_sg_display;
 
 extern uint amdgpu_user_partt_mode;
 
+extern int gart_ram_alloc;
+
 #define AMDGPU_VM_MAX_NUM_CTX			4096
 #define AMDGPU_SG_THRESHOLD			(256*1024*1024)
 #define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 13bcd8e955ac..d972f77b506b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -812,6 +812,14 @@ bool debug_evictions;
 module_param(debug_evictions, bool, 0644);
 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
 
+/**
+ * DOC: gart_ram_alloc (int)
+ * Force the gart page table to be created in the system memory instead of VRAM
+ */
+int gart_ram_alloc = 1;
+module_param(gart_ram_alloc, int, 0644);
+MODULE_PARM_DESC(gart_ram_alloc, "Force allocate GART on system memory (1 = default)");
+
 /**
  * DOC: no_system_mem_limit(bool)
  * Disable system memory limit, to support multiple process shared memory
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 8901e73fd700..58f0ff1c6035 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -253,7 +253,7 @@ static void gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev,
 
 		tmp = regVM_L2_CNTL4_DEFAULT;
 		/* For AMD APP APUs setup WC memory */
-		if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {
+		if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu || gart_ram_alloc) {
 			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 		} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 53bd7506ff22..5c9a0f3d5581 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1670,7 +1670,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
 				 AMDGPU_PTE_EXECUTABLE;
 
-	if (!adev->gmc.real_vram_size) {
+	if (!adev->gmc.real_vram_size || gart_ram_alloc) {
 		dev_info(adev->dev, "Put GART in system memory for APU\n");
 		r = amdgpu_gart_table_ram_alloc(adev);
 		if (r)
@@ -1890,7 +1890,7 @@ static int gmc_v9_0_sw_fini(void *handle)
 	amdgpu_gmc_ras_fini(adev);
 	amdgpu_gem_force_release(adev);
 	amdgpu_vm_manager_fini(adev);
-	if (!adev->gmc.real_vram_size) {
+	if (!adev->gmc.real_vram_size || gart_ram_alloc) {
 		dev_info(adev->dev, "Put GART in system memory for APU free\n");
 		amdgpu_gart_table_ram_free(adev);
 	} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index a8faf66b6878..b18bb3773f77 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -258,7 +258,7 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
 
 		tmp = regVM_L2_CNTL4_DEFAULT;
 		/* For AMD APP APUs setup WC memory */
-		if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {
+		if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu || gart_ram_alloc) {
 			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 					    VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
-- 
2.39.2