[PATCH v3 6/6] drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v4_0

[Zhou1, Tao]

[AMD Official Use Only - General]

The series is:

Reviewed-by: Tao Zhou <tao.zhou1 at amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Horatio
> Zhang
> Sent: Tuesday, May 16, 2023 1:04 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Liu, HaoPing (Alan) <HaoPing.Liu at amd.com>; Zhou, Bob
> <Bob.Zhou at amd.com>; Zhang, Horatio <Hongkun.Zhang at amd.com>; Xu, Feifei
> <Feifei.Xu at amd.com>; Zhou1, Tao <Tao.Zhou1 at amd.com>; Jiang, Sonny
> <Sonny.Jiang at amd.com>; Limonciello, Mario <Mario.Limonciello at amd.com>;
> Liu, Leo <Leo.Liu at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>
> Subject: [PATCH v3 6/6] drm/amdgpu: add RAS POISON interrupt funcs for
> jpeg_v4_0
> 
> Add ras_poison_irq and functions. And fix the amdgpu_irq_put call trace in
> jpeg_v4_0_hw_fini.
> 
> [   50.497562] RIP: 0010:amdgpu_irq_put+0xa4/0xc0 [amdgpu]
> [   50.497619] RSP: 0018:ffffaa2400fcfcb0 EFLAGS: 00010246
> [   50.497620] RAX: 0000000000000000 RBX: 0000000000000001 RCX:
> 0000000000000000
> [   50.497621] RDX: 0000000000000000 RSI: 0000000000000000 RDI:
> 0000000000000000
> [   50.497621] RBP: ffffaa2400fcfcd0 R08: 0000000000000000 R09:
> 0000000000000000
> [   50.497622] R10: 0000000000000000 R11: 0000000000000000 R12:
> ffff99b2105242d8
> [   50.497622] R13: 0000000000000000 R14: ffff99b210500000 R15:
> ffff99b210500000
> [   50.497623] FS:  0000000000000000(0000) GS:ffff99b518480000(0000)
> knlGS:0000000000000000
> [   50.497623] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [   50.497624] CR2: 00007f9d32aa91e8 CR3: 00000001ba210000 CR4:
> 0000000000750ee0
> [   50.497624] PKRU: 55555554
> [   50.497625] Call Trace:
> [   50.497625]  <TASK>
> [   50.497627]  jpeg_v4_0_hw_fini+0x43/0xc0 [amdgpu]
> [   50.497693]  jpeg_v4_0_suspend+0x13/0x30 [amdgpu]
> [   50.497751]  amdgpu_device_ip_suspend_phase2+0x240/0x470 [amdgpu]
> [   50.497802]  amdgpu_device_ip_suspend+0x41/0x80 [amdgpu]
> [   50.497854]  amdgpu_device_pre_asic_reset+0xd9/0x4a0 [amdgpu]
> [   50.497905]  amdgpu_device_gpu_recover.cold+0x548/0xcf1 [amdgpu]
> [   50.498005]  amdgpu_debugfs_reset_work+0x4c/0x80 [amdgpu]
> [   50.498060]  process_one_work+0x21f/0x400
> [   50.498063]  worker_thread+0x200/0x3f0
> [   50.498064]  ? process_one_work+0x400/0x400
> [   50.498065]  kthread+0xee/0x120
> [   50.498067]  ? kthread_complete_and_exit+0x20/0x20
> [   50.498068]  ret_from_fork+0x22/0x30
> 
> Suggested-by: Hawking Zhang <Hawking.Zhang at amd.com>
> Signed-off-by: Horatio Zhang <Hongkun.Zhang at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 27 +++++++++++++++++++-------
>  1 file changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index 495facb885f4..8690467b3285 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -87,13 +87,13 @@ static int jpeg_v4_0_sw_init(void *handle)
> 
>  	/* JPEG DJPEG POISON EVENT */
>  	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
> -			VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst-
> >irq);
> +			VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst-
> >ras_poison_irq);
>  	if (r)
>  		return r;
> 
>  	/* JPEG EJPEG POISON EVENT */
>  	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
> -			VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst-
> >irq);
> +			VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst-
> >ras_poison_irq);
>  	if (r)
>  		return r;
> 
> @@ -202,7 +202,8 @@ static int jpeg_v4_0_hw_fini(void *handle)
>  			RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
>  			jpeg_v4_0_set_powergating_state(adev,
> AMD_PG_STATE_GATE);
>  	}
> -	amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0);
> +	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
> +		amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
> 
>  	return 0;
>  }
> @@ -670,6 +671,14 @@ static int jpeg_v4_0_set_interrupt_state(struct
> amdgpu_device *adev,
>  	return 0;
>  }
> 
> +static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
> +					struct amdgpu_irq_src *source,
> +					unsigned int type,
> +					enum amdgpu_interrupt_state state) {
> +	return 0;
> +}
> +
>  static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
>  				      struct amdgpu_irq_src *source,
>  				      struct amdgpu_iv_entry *entry) @@ -680,10
> +689,6 @@ static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
>  	case VCN_4_0__SRCID__JPEG_DECODE:
>  		amdgpu_fence_process(adev->jpeg.inst->ring_dec);
>  		break;
> -	case VCN_4_0__SRCID_DJPEG0_POISON:
> -	case VCN_4_0__SRCID_EJPEG0_POISON:
> -		amdgpu_jpeg_process_poison_irq(adev, source, entry);
> -		break;
>  	default:
>  		DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
>  			  entry->src_id, entry->src_data[0]); @@ -753,10
> +758,18 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {
>  	.process = jpeg_v4_0_process_interrupt,  };
> 
> +static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = {
> +	.set = jpeg_v4_0_set_ras_interrupt_state,
> +	.process = amdgpu_jpeg_process_poison_irq, };
> +
>  static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev)  {
>  	adev->jpeg.inst->irq.num_types = 1;
>  	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
> +
> +	adev->jpeg.inst->ras_poison_irq.num_types = 1;
> +	adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
>  }
> 
>  const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = {
> --
> 2.34.1