[PATCH v4] drm/amd: Flush any delayed gfxoff on suspend entry

[Quan, Evan]

[AMD Official Use Only - General]

If I understand correctly, similar job is already performed in "amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);"
Maybe you just need to undo the "skip PG for GFX on S0ix"?

                /* skip PG for GFX, SDMA on S0ix */
                if (adev->in_s0ix &&
                    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
                        continue;

Evan
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Mario
> Limonciello
> Sent: Friday, May 19, 2023 12:53 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Tsao, Anson <anson.tsao at amd.com>; Huang, Tim
> <Tim.Huang at amd.com>; Martinez, Juan <Juan.Martinez at amd.com>;
> Limonciello, Mario <Mario.Limonciello at amd.com>; Gong, Richard
> <Richard.Gong at amd.com>
> Subject: [PATCH v4] drm/amd: Flush any delayed gfxoff on suspend entry
>
> DCN 3.1.4 is reported to hang on s2idle entry if graphics activity
> is happening during entry.  This is because GFXOFF was scheduled as
> delayed but RLC gets disabled in s2idle entry sequence which will
> hang GFX IP if not already in GFXOFF.
>
> To help this problem, flush any delayed work for GFXOFF early in
> s2idle entry sequence to ensure that it's off when RLC is changed.
>
> commit 3964b0c2e843 ("drm/amdgpu: complete gfxoff allow signal during
> suspend without delay") modified power gating flow so that if called
> in s0ix that it ensured that GFXOFF wasn't put in work queue but
> instead processed immediately.
>
> This is dead code due to commit 5d70a549d00d ("drm/amdgpu: skip
> CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly
> called as part of the suspend entry code.  Remove that dead code.
>
> Cc: stable at vger.kernel.org # 6.1+
> Suggested-by: Tim Huang <tim.huang at amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>
> ---
> v3->v4:
>  * Drop patches 2-4
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c    | 9 +--------
>  2 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a9d9bbe8586b..059139f1f973 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4316,6 +4316,7 @@ int amdgpu_device_suspend(struct drm_device
> *dev, bool fbcon)
>               drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)-
> >fb_helper, true);
>
>       cancel_delayed_work_sync(&adev->delayed_init_work);
> +     flush_delayed_work(&adev->gfx.gfx_off_delay_work);
>
>       amdgpu_ras_suspend(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index f2d0b1d55d77..b1190eb0e9c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -692,15 +692,8 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device
> *adev, bool enable)
>
>               if (adev->gfx.gfx_off_req_count == 0 &&
>                   !adev->gfx.gfx_off_state) {
> -                     /* If going to s2idle, no need to wait */
> -                     if (adev->in_s0ix) {
> -                             if
> (!amdgpu_dpm_set_powergating_by_smu(adev,
> -                                             AMD_IP_BLOCK_TYPE_GFX,
> true))
> -                                     adev->gfx.gfx_off_state = true;
> -                     } else {
> -                             schedule_delayed_work(&adev-
> >gfx.gfx_off_delay_work,
> +                     schedule_delayed_work(&adev-
> >gfx.gfx_off_delay_work,
>                                             delay);
> -                     }
>               }
>       } else {
>               if (adev->gfx.gfx_off_req_count == 0) {
> --
> 2.34.1