[PATCH] drm/amdgpu: correct mca ipid die/socket/addr decode

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Wang, Yang(Kevin) <KevinYang.Wang at amd.com>
Sent: Friday, November 10, 2023 14:33
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Wang, Yang(Kevin) <KevinYang.Wang at amd.com>
Subject: [PATCH] drm/amdgpu: correct mca ipid die/socket/addr decode

correct mca ipid die/socket/addr decode

Signed-off-by: Yang Wang <kevinyang.wang at amd.com>
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c    | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 789552c66d1d..3f71490b779c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2381,8 +2381,8 @@ static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT

 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)  {
-       uint64_t ipid = entry->regs[MCA_REG_IDX_IPID];
-       uint32_t insthi;
+       u64 ipid = entry->regs[MCA_REG_IDX_IPID];
+       u32 instidhi, instid;

        /* NOTE: All MCA IPID register share the same format,
         * so the driver can share the MCMP1 register header file.
@@ -2391,9 +2391,14 @@ static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_
        info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
        info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);

-       insthi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
-       info->aid = ((insthi >> 2) & 0x03);
-       info->socket_id = insthi & 0x03;
+       /* Unfied DieID Format: SAASS. A:AID, S:Socket.
+        * Unfied DieID[4] = InstanceId[0]
+        * Unfied DieID[0:3] = InstanceIdHi[0:3]
+        * */
+       instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
+       instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
+       info->aid = ((instidhi >> 2) & 0x03);
+       info->socket_id = ((instid & 0x1) << 4) | (instidhi & 0x03);
 }

 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, @@ -2567,6 +2572,7 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct
        uint32_t instlo;

        instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
+       instlo &= GENMASK(31, 1);
        switch (instlo) {
        case 0x36430400: /* SMNAID XCD 0 */
        case 0x38430400: /* SMNAID XCD 1 */
@@ -2585,6 +2591,7 @@ static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amd
        uint32_t errcode, instlo;

        instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
+       instlo &= GENMASK(31, 1);
        if (instlo != 0x03b30400)
                return false;

--
2.34.1