[PATCH 1/2] drm/amd: Update `update_pcie_parameters` functions to use uint8_t arguments

[Christian König]

Am 30.09.23 um 05:22 schrieb Mario Limonciello:
> The matching values for `pcie_gen_cap` and `pcie_width_cap` when
> fetched from powerplay tables are 1 byte, so narrow the arguments
> to match to ensure min() and max() comparisons without casts.
>
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>

Acked-by: Christian König <christian.koenig at amd.com> for the series.

> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c               | 2 +-
>   drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h           | 2 +-
>   drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h            | 4 ++--
>   drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c         | 4 ++--
>   drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 ++++----
>   drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c          | 4 ++--
>   6 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 33eaf0d77163..99750c182279 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1270,7 +1270,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
>   {
>   	struct smu_feature *feature = &smu->smu_feature;
>   	struct amdgpu_device *adev = smu->adev;
> -	uint32_t pcie_gen = 0, pcie_width = 0;
> +	uint8_t pcie_gen = 0, pcie_width = 0;
>   	uint64_t features_supported;
>   	int ret = 0;
>   
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index 4f6df3558b9b..f3cab5e633a7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -846,7 +846,7 @@ struct pptable_funcs {
>   	 * &pcie_gen_cap: Maximum allowed PCIe generation.
>   	 * &pcie_width_cap: Maximum allowed PCIe width.
>   	 */
> -	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
> +	int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);
>   
>   	/**
>   	 * @i2c_init: Initialize i2c.
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> index 355c156d871a..cc02f979e9e9 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> @@ -296,8 +296,8 @@ int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
>   					uint32_t pptable_id);
>   
>   int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
> -				     uint32_t pcie_gen_cap,
> -				     uint32_t pcie_width_cap);
> +				     uint8_t pcie_gen_cap,
> +				     uint8_t pcie_width_cap);
>   
>   #endif
>   #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 650482cedd1f..5f3cbfff156a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -2380,8 +2380,8 @@ static int navi10_get_power_limit(struct smu_context *smu,
>   }
>   
>   static int navi10_update_pcie_parameters(struct smu_context *smu,
> -				     uint32_t pcie_gen_cap,
> -				     uint32_t pcie_width_cap)
> +					 uint8_t pcie_gen_cap,
> +					 uint8_t pcie_width_cap)
>   {
>   	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
>   	PPTable_t *pptable = smu->smu_table.driver_pptable;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 1f05bfb7d473..dd07662262e4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -2092,14 +2092,14 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
>   #define MAX(a, b)	((a) > (b) ? (a) : (b))
>   
>   static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
> -					 uint32_t pcie_gen_cap,
> -					 uint32_t pcie_width_cap)
> +						 uint8_t pcie_gen_cap,
> +						 uint8_t pcie_width_cap)
>   {
>   	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
>   	struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
>   	uint8_t *table_member1, *table_member2;
> -	uint32_t min_gen_speed, max_gen_speed;
> -	uint32_t min_lane_width, max_lane_width;
> +	uint8_t min_gen_speed, max_gen_speed;
> +	uint8_t min_lane_width, max_lane_width;
>   	uint32_t smu_pcie_arg;
>   	int ret, i;
>   
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index d86499ac8931..208db8b580eb 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -2419,8 +2419,8 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
>   }
>   
>   int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
> -				     uint32_t pcie_gen_cap,
> -				     uint32_t pcie_width_cap)
> +				     uint8_t pcie_gen_cap,
> +				     uint8_t pcie_width_cap)
>   {
>   	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
>   	struct smu_13_0_pcie_table *pcie_table =