[PATCH 01/16] drm/amd/display: Modify SMU message logs

[Tom Chung]

From: Sung Joon Kim <sungkim at amd.com>

[why]
It's important to make sure SMU messages
are logged by default to improve debugging for
power optimization use cases.

[how]
Change logs to warnings when SMU message
returns non-success id.

Reviewed-by: Charlene Liu <charlene.liu at amd.com>
Acked-by: Tom Chung <chiahsuan.chung at amd.com>
Signed-off-by: Sung Joon Kim <sungkim at amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c |  1 +
 .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 12 ++++++------
 drivers/gpu/drm/amd/display/dc/dc.h                  |  1 +
 drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c |  1 +
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index b5acd7b01e40..21dfe3faf08c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -1046,6 +1046,7 @@ void dcn35_clk_mgr_construct(
 			ctx->dc->debug.disable_dpp_power_gate = false;
 			ctx->dc->debug.disable_hubp_power_gate = false;
 			ctx->dc->debug.disable_dsc_power_gate = false;
+			ctx->dc->debug.disable_hpo_power_gate = false;
 		} else {
 			/*let's reset the config control flag*/
 			ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index cf74e69cb2a1..b6b8c3ca1572 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -130,11 +130,11 @@ static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	if (result != VBIOSSMC_Result_OK) {
+		DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
 
-
-	if (result == VBIOSSMC_Status_BUSY) {
-		smu_print("SMU response after wait: %d\n", result);
-		return -1;
+		if (result == VBIOSSMC_Status_BUSY)
+			return -1;
 	}
 
 	/* First clear response register */
@@ -155,7 +155,7 @@ static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 		else
 			ASSERT(0);
 		REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
-		smu_print("SMU response after wait: %d\n", result);
+		DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
 		return -1;
 	}
 
@@ -163,7 +163,7 @@ static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 		ASSERT(0);
 		result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);
 		//dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
-		smu_print("SMU response after wait: %d\n", result);
+		DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id);
 	}
 
 	return REG_READ(MP1_SMN_C2PMSG_83);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7d1ce58d493b..6c51ebf5bbad 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -830,6 +830,7 @@ struct dc_debug_options {
 	bool disable_hubp_power_gate;
 	bool disable_dsc_power_gate;
 	bool disable_optc_power_gate;
+	bool disable_hpo_power_gate;
 	int dsc_min_slice_height_override;
 	int dsc_bpp_increment_div;
 	bool disable_pplib_wm_range;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
index ccfd3102e5a0..e62a192c595e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
@@ -262,6 +262,7 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)
 	bool block_enabled;
 
 	if (pg_cntl->ctx->dc->debug.ignore_pg ||
+		pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||
 		pg_cntl->ctx->dc->idle_optimizations_allowed)
 		return;
 
-- 
2.25.1