[PATCH 01/26] drm/amd/display: remove duplicated edp relink to fastboot

[Roman.Li at amd.com]

From: Chiawen Huang <chiawen.huang at amd.com>

[Why&How]
enable_accelerated_mode function is fully to check
whether fastboot support or not.
It is no longer to disable_vbios_mode_if_required.
enable_stream_timing is allowed when seamless/fast
boot are disabled.

Reviewed-by: Charlene Liu <charlene.liu at amd.com>
Acked-by: Roman Li <roman.li at amd.com>
Signed-off-by: Chiawen Huang <chiawen.huang at amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 62 -------------------
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  8 ++-
 2 files changed, 5 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f602ff0d4146..49e31bd52992 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1215,67 +1215,6 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 	dc_release_state(current_ctx);
 }
 
-static void disable_vbios_mode_if_required(
-		struct dc *dc,
-		struct dc_state *context)
-{
-	unsigned int i, j;
-
-	/* check if timing_changed, disable stream*/
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct dc_stream_state *stream = NULL;
-		struct dc_link *link = NULL;
-		struct pipe_ctx *pipe = NULL;
-
-		pipe = &context->res_ctx.pipe_ctx[i];
-		stream = pipe->stream;
-		if (stream == NULL)
-			continue;
-
-		if (stream->apply_seamless_boot_optimization)
-			continue;
-
-		// only looking for first odm pipe
-		if (pipe->prev_odm_pipe)
-			continue;
-
-		if (stream->link->local_sink &&
-			stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
-			link = stream->link;
-		}
-
-		if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
-			unsigned int enc_inst, tg_inst = 0;
-			unsigned int pix_clk_100hz;
-
-			enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
-			if (enc_inst != ENGINE_ID_UNKNOWN) {
-				for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
-					if (dc->res_pool->stream_enc[j]->id == enc_inst) {
-						tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
-							dc->res_pool->stream_enc[j]);
-						break;
-					}
-				}
-
-				dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
-					dc->res_pool->dp_clock_source,
-					tg_inst, &pix_clk_100hz);
-
-				if (link->link_status.link_active) {
-					uint32_t requested_pix_clk_100hz =
-						pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
-
-					if (pix_clk_100hz != requested_pix_clk_100hz) {
-						dc->link_srv->set_dpms_off(pipe);
-						pipe->stream->dpms_off = false;
-					}
-				}
-			}
-		}
-	}
-}
-
 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 {
 	int i;
@@ -1845,7 +1784,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 		dc_streams[i] =  context->streams[i];
 
 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
-		disable_vbios_mode_if_required(dc, context);
 		dc->hwss.enable_accelerated_mode(dc, context);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 74602a5fd6dd..8bf7d36ff092 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1546,8 +1546,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 	 */
 	if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
 		/*  */
-		/* Do not touch stream timing on seamless boot optimization. */
-		if (!pipe_ctx->stream->apply_seamless_boot_optimization)
+		/* Do not touch stream timing on seamless/fast boot optimization. */
+		if (!pipe_ctx->stream->apply_seamless_boot_optimization &&
+			!pipe_ctx->stream->apply_edp_fast_boot_optimization)
 			hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
 
 	if (hws->funcs.setup_vupdate_interrupt)
@@ -1587,7 +1588,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 	 * function core_link_enable_stream
 	 */
 	if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
-		if (!pipe_ctx->stream->apply_seamless_boot_optimization)
+		if (!pipe_ctx->stream->apply_seamless_boot_optimization &&
+			!pipe_ctx->stream->apply_edp_fast_boot_optimization)
 			hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
 	}
 
-- 
2.34.1