[PATCH 12/28] drm/amd/display: Add new logs for AutoDPMTest
Stylon Wang
stylon.wang at amd.com
Wed Sep 6 12:28:17 UTC 2023
From: Ethan Bitnun <etbitnun at amd.com>
[Description]
- Add new logs to be used by the AutoDPMTest
- Enclose AutoDPMTest logs in settings
- Add logging definition
Reviewed-by: Alvin Lee <alvin.lee2 at amd.com>
Acked-by: Stylon Wang <stylon.wang at amd.com>
Signed-off-by: Ethan Bitnun <etbitnun at amd.com>
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 36 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/include/logger_types.h | 5 ++-
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 984b52923534..4fd25bb1ab92 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -450,6 +450,38 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
return 0;
}
+static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr_internal *clk_mgr)
+{
+ ////////////////////////////////////////////////////////////////////////////
+ // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
+ // anywhere other than at the very end of the string.
+ //
+ // Formatting example (make sure to have " - " between each entry):
+ //
+ // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
+ ////////////////////////////////////////////////////////////////////////////
+ if (new_clocks &&
+ new_clocks->dramclk_khz > 0 &&
+ new_clocks->fclk_khz > 0 &&
+ new_clocks->dcfclk_khz > 0 &&
+ new_clocks->dppclk_khz > 0) {
+
+ if (new_clocks->p_state_change_support) {
+ DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:%d - fclk_khz:%d - "
+ "dcfclk_khz:%d - dppclk_khz:%d\n",
+ new_clocks->dramclk_khz,
+ new_clocks->fclk_khz,
+ new_clocks->dcfclk_khz,
+ new_clocks->dppclk_khz);
+ } else {
+ DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:1249000 - fclk_khz:%d - "
+ "dcfclk_khz:%d - dppclk_khz:%d\n",
+ new_clocks->fclk_khz,
+ new_clocks->dcfclk_khz,
+ new_clocks->dppclk_khz);
+ }
+ }
+}
static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
@@ -646,6 +678,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
/*update dmcu for wait_loop count*/
dmcu->funcs->set_psr_wait_loop(dmcu,
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
+
+ if (dc->config.enable_auto_dpm_test_logs) {
+ dcn32_auto_dpm_test_log(new_clocks, clk_mgr);
+ }
}
static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7e6f819a9952..05ab24c81041 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -420,6 +420,7 @@ struct dc_config {
int sdpif_request_limit_words_per_umc;
bool use_old_fixed_vs_sequence;
bool dc_mode_clk_limit_support;
+ bool enable_auto_dpm_test_logs;
};
enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 3bf08a60c45c..fb657f7408a7 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -73,6 +73,7 @@
#define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__)
#define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
#define DC_LOG_DP2(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_AUTO_DPM_TEST(...) pr_debug("[AutoDPMTest]: "__VA_ARGS__)
struct dal_logger;
@@ -128,6 +129,7 @@ enum dc_log_type {
LOG_SAMPLE_1DLUT,
LOG_DP2,
LOG_DC2RESERVED12,
+ LOG_AUTO_DPM_TEST,
};
#define DC_MIN_LOG_MASK ((1 << LOG_ERROR) | \
@@ -157,7 +159,8 @@ enum dc_log_type {
(1ULL << LOG_IF_TRACE) | \
(1ULL << LOG_HDMI_FRL) | \
(1ULL << LOG_SCALER) | \
- (1ULL << LOG_DTN) /* | \
+ (1ULL << LOG_DTN) | \
+ (1ULL << LOG_AUTO_DPM_TEST)/* | \
(1ULL << LOG_DEBUG) | \
(1ULL << LOG_BIOS) | \
(1ULL << LOG_SURFACE) | \
--
2.42.0
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