[bug report] drm/amd/display: Add DCN35 CLK_MGR

[Dan Carpenter]

Hello Qingqing Zhuo,

This is a semi-automatic email about new static checker warnings.

The patch 8774029f76b9: "drm/amd/display: Add DCN35 CLK_MGR" from Aug
2, 2023, leads to the following Smatch complaint:

    drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:980 dcn35_clk_mgr_construct()
    warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 913)

drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
   912	
   913			if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
                            ^^^^^^^^^^^^
Unchecked dereference.  Also why is does AMD code have weird indenting
like this?  It's totally unique to AMD.  I guess there was an if
statement which was deleted or maybe this is autogenerated somehow?

   914				dcn35_bw_params.wm_table = lpddr5_wm_table;
   915			} else {
   916				dcn35_bw_params.wm_table = ddr5_wm_table;
   917			}
   918			/* Saved clocks configured at boot for debug purposes */
   919			 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
   920	
   921		clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
   922		clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base);
   923	
   924		if (!clk_mgr->base.base.clks.ref_dtbclk_khz)
   925			dcn35_smu_set_dtbclk(&clk_mgr->base, true);
   926	
   927		clk_mgr->base.base.clks.dtbclk_en = true;
   928		dce_clock_read_ss_info(&clk_mgr->base);
   929		/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
   930	
   931		dcn35_read_ss_info_from_lut(&clk_mgr->base);
   932		clk_mgr->base.base.dprefclk_khz =
   933			dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
   934	
   935		clk_mgr->base.base.bw_params = &dcn35_bw_params;
   936	
   937		if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
   938			int i;
   939			dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
   940			DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
   941					   "NumDispClkLevelsEnabled: %d\n"
   942					   "NumSocClkLevelsEnabled: %d\n"
   943					   "VcnClkLevelsEnabled: %d\n"
   944					   "NumDfPst atesEnabled: %d\n"
   945					   "MinGfxClk: %d\n"
   946					   "MaxGfxClk: %d\n",
   947					   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
   948					   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
   949					   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
   950					   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
   951					   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
   952					   smu_dpm_clks.dpm_clks->MinGfxClk,
   953					   smu_dpm_clks.dpm_clks->MaxGfxClk);
   954			for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
   955				DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
   956						   i,
   957						   smu_dpm_clks.dpm_clks->DcfClocks[i]);
   958			}
   959			for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
   960				DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
   961						   i, smu_dpm_clks.dpm_clks->DispClocks[i]);
   962			}
   963			for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
   964				DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
   965						   i, smu_dpm_clks.dpm_clks->SocClocks[i]);
   966			}
   967			for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
   968				DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
   969						   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
   970	
   971			for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
   972				DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
   973						   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
   974						   "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
   975						   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
   976						   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
   977						   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
   978			}
   979	
   980			if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
                            ^^^^^^^^^^^^
This NULL check is too late.  It will already have crashed.

   981				dcn35_clk_mgr_helper_populate_bw_params(
   982						&clk_mgr->base,

regards,
dan carpenter