[PATCH 4/4] drm/amd: Enable seamless boot by default on newer APUs

[Harry Wentland]

On 2023-09-05 16:13, Mario Limonciello wrote:
> On 9/5/2023 15:07, Deucher, Alexander wrote:
>> [Public]
>>
>>> -----Original Message-----
>>> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Mario
>>> Limonciello
>>> Sent: Tuesday, September 5, 2023 3:26 PM
>>> To: amd-gfx at lists.freedesktop.org
>>> Cc: Limonciello, Mario <Mario.Limonciello at amd.com>
>>> Subject: [PATCH 4/4] drm/amd: Enable seamless boot by default on newer
>>> APUs
>>>
>>> IP discovery is a good line in the sand to expand seamless boot to 
>>> more ASICs.
>>>
>>> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++-------
>>>   1 file changed, 3 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index 9159a7b993ab..19265dbe592e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -1296,14 +1296,10 @@ bool amdgpu_seamless_boot_supported(struct
>>> amdgpu_device *adev)
>>>        if (adev->mman.keep_stolen_vga_memory)
>>>                return false;
>>
>> This probably needs to be revisited too.  I don't know why this is an 
>> issue.  This flag just means the kernel driver keeps the stolen VGA 
>> region as reserved rather than releasing it back into the pool of 
>> available memory.  I don't think it should directly affect this feature.
>>
>>>
>>> -     switch (adev->ip_versions[DCE_HWIP][0]) {
>>> -     case IP_VERSION(3, 0, 1):
>>> -             return true;
>>> -     default:
>>> -             break;
>>> -     }
>>> +     if (adev->asic_type != CHIP_IP_DISCOVERY)
>>> +             return false;
>>
>> Probably need input from the display team, but I think a number of the 
>> older chips we'd probably want this too.  Maybe base it on the 
>> DCE_HWIP version?  DCN 1.0.0 or newer?  Or maybe  DCN 3.0.0 or newer?
>>
> 
> I think it will only work on the older chips if the 
> adev->mman.keep_stolen_vga_memory check can actually be dropped as some 
> of the older chips explicitly set it to TRUE.
> 
> There are other non-obvious dependencies too like:
> f0882d3afb9a ("drm/amd/display: prevent seamless boot on displays that 
> don't have the preferred dig")
> 6349c73859cb ("drm/amd/display: For ODM seamless transition require AUTO 
> mode")
> 
> So I was trying to be cautious in just enabling a few more things right 
> now.  I think essentially this "only" enables for for Rembrandt, 
> Raphael, Mendocino and Phoenix.  I tested it on Phoenix and Rembrandt.
> 
> But the module parameter is an escape hatch.  Let's see what display 
> team says.
> 

The core code around this should support DCN1+ and DC has logic to check
whether we can actually do a seamless handover 
(mark_seamless_boot_stream). If it's not possible we'll still reprogram
the output (as in the case of that first patch you mention above).

Not sure about the stolen_vga_memory thing. But that's a question
separately from the ASIC generations supported.

I'd be fine to allow seamless boot for DCN1+. Though would it be 
considered a regression if we had to roll this back and only allow
it for newer ASICs? In that case maybe DCN3+ is a good cutoff.

Patches 2 and 3 (with Alex's comment addressed) are
Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry


>>>
>>> -     return false;
>>> +     return adev->flags & AMD_IS_APU;
>>>   }
>>>
>>>   /*
>>> -- 
>>> 2.34.1
>>
>