[PATCH 12/28] drm/amd/display: STREAM_MAPPER_CONTROL register offset on DCN35

[Rodrigo Siqueira]

From: Artem Grishin <artem.grishin at amd.com>

[Why]
The STREAM_MAPPER_CONTROL register offset was left uninitialized,
causing warning in the driver log at runtime

[How]
A temporary solution to add it into dcn35_create_resource_pool.

[TODO]
Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h
and SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h

Reviewed-by: Charlene Liu <charlene.liu at amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo at amd.com>
Signed-off-by: Artem Grishin <artem.grishin at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
index 00e2216b6205..5ec70d46a38f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
@@ -137,7 +137,8 @@ struct resource_pool *dcn35_create_resource_pool(
 	SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \
 	SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \
 	SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \
-	SRI_ARR(DIG_FIFO_CTRL0, DIG, id)
+	SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
+	SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)
 
 #define LE_DCN35_REG_LIST_RI(id)\
 	LE_DCN3_REG_LIST_RI(id),\
-- 
2.40.1