[PATCH] drm/amd/display: Remove unused DPCD declarations

[Harry Wentland]

On 2023-09-22 05:58, Stylon Wang wrote:
> [Why & How]
> These DPCD addresses are either declared in other header files
> where it makes more sense or simply not used by any DC code.
> Remove them to reduce redundancies and potential confusion.
> 
> Signed-off-by: Stylon Wang <stylon.wang at amd.com>

Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry

> ---
>   drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 59 +-------------------
>   1 file changed, 1 insertion(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> index cfaa39c5dd16..35ae245ef722 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> @@ -916,73 +916,16 @@ struct dpcd_usb4_dp_tunneling_info {
>   	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
>   };
>   
> -#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
> -#define DP_MAIN_LINK_CHANNEL_CODING_CAP			0x006
> -#endif
> -#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
> -#define DP_SINK_VIDEO_FALLBACK_FORMATS			0x020
> -#endif
> -#ifndef DP_FEC_CAPABILITY_1
> -#define DP_FEC_CAPABILITY_1				0x091
> -#endif
>   #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
>   #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT		0x0A3
>   #endif
> -#ifndef DP_DSC_CONFIGURATION
> -#define DP_DSC_CONFIGURATION				0x161
> -#endif
> -#ifndef DP_PHY_SQUARE_PATTERN
> -#define DP_PHY_SQUARE_PATTERN				0x249
> -#endif
> -#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
> -#define DP_128b_132b_SUPPORTED_LINK_RATES		0x2215
> -#endif
> -#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
> -#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL		0x2216
> -#endif
>   #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
>   #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0		0X2230
>   #endif
>   #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
>   #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256		0X2250
>   #endif
> -#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
> -#define DP_DSC_SUPPORT_AND_DECODER_COUNT		0x2260
> -#endif
> -#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
> -#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0	0x2270
> -#endif
> -#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
> -#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK	(1 << 0)
> -#endif
> -#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
> -#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK	(0b111 << 1)
> -#endif
> -#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
> -#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT	1
> -#endif
> -#ifndef DP_DSC_DECODER_COUNT_MASK
> -#define DP_DSC_DECODER_COUNT_MASK			(0b111 << 5)
> -#endif
> -#ifndef DP_DSC_DECODER_COUNT_SHIFT
> -#define DP_DSC_DECODER_COUNT_SHIFT			5
> -#endif
> -#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
> -#define DP_MAIN_LINK_CHANNEL_CODING_SET			0x108
> -#endif
> -#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
> -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER	0xF0006
> -#endif
> -#ifndef DP_PHY_REPEATER_128b_132b_RATES
> -#define DP_PHY_REPEATER_128b_132b_RATES			0xF0007
> -#endif
> -#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
> -#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	0xF0022
> -#endif
> -#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
> -#define DP_INTRA_HOP_AUX_REPLY_INDICATION		(1 << 3)
> -/* TODO - Use DRM header to replace above once available */
> -#endif // DP_INTRA_HOP_AUX_REPLY_INDICATION
> +
>   union dp_main_line_channel_coding_cap {
>   	struct {
>   		uint8_t DP_8b_10b_SUPPORTED	:1;