[PATCH] drm/amdgpu: Fix the ring buffer size for queue VM flush

[Christian König]

Am 26.03.24 um 09:21 schrieb Prike Liang:
> Here are the corrections needed for the queue ring buffer size
> calculation for the following cases:
> - Remove the KIQ VM flush ring usage.
> - Add the invalidate TLBs packet for gfx10 and gfx11 queue.
> - There's no VM flush and PFP sync, so remove the gfx9 real
>    ring and compute ring buffer usage.
>
> Signed-off-by: Prike Liang <Prike.Liang at amd.com>

Good catch, that was probably just copied over from the gfx implementation.

When the function isn't used with the compute rings any more you can 
probably also remove this from gfx_v9_0_ring_emit_vm_flush():

         /* compute doesn't have PFP */
         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

With or without that the patch is Reviewed-by: Christian König 
<christian.koenig at amd.com>.

Thanks,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +--
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +--
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 5 -----
>   3 files changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index d524f1a353ed..0c7312c0fa7f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9186,7 +9186,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>   		7 + /* PIPELINE_SYNC */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* VM_FLUSH */
> +		4 + /* VM_FLUSH */
>   		8 + /* FENCE for VM_FLUSH */
>   		20 + /* GDS switch */
>   		4 + /* double SWITCH_BUFFER,
> @@ -9276,7 +9276,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
>   		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* gfx_v10_0_ring_emit_vm_flush */
>   		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
>   	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
>   	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7a906318e451..5390dd2c51da 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -6191,7 +6191,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
>   		7 + /* PIPELINE_SYNC */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* VM_FLUSH */
> +		4 + /* VM_FLUSH */
>   		8 + /* FENCE for VM_FLUSH */
>   		20 + /* GDS switch */
>   		5 + /* COND_EXEC */
> @@ -6277,7 +6277,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
>   		7 + /* gfx_v11_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* gfx_v11_0_ring_emit_vm_flush */
>   		8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
>   	.emit_ib_size =	7, /* gfx_v11_0_ring_emit_ib_compute */
>   	.emit_ib = gfx_v11_0_ring_emit_ib_compute,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 71b555993b7a..fce0b8238d13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6872,7 +6872,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>   		7 +  /* PIPELINE_SYNC */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* VM_FLUSH */
>   		8 +  /* FENCE for VM_FLUSH */
>   		20 + /* GDS switch */
>   		4 + /* double SWITCH_BUFFER,
> @@ -6892,7 +6891,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>   	.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
>   	.emit_fence = gfx_v9_0_ring_emit_fence,
>   	.emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
> -	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
>   	.test_ring = gfx_v9_0_ring_test_ring,
> @@ -6981,7 +6979,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
>   		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* gfx_v9_0_ring_emit_vm_flush */
>   		8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
>   		7 + /* gfx_v9_0_emit_mem_sync */
>   		5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
> @@ -6990,7 +6987,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
>   	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
>   	.emit_fence = gfx_v9_0_ring_emit_fence,
>   	.emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
> -	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
>   	.test_ring = gfx_v9_0_ring_test_ring,
> @@ -7019,7 +7015,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
>   		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
>   		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> -		2 + /* gfx_v9_0_ring_emit_vm_flush */
>   		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
>   	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */
>   	.emit_fence = gfx_v9_0_ring_emit_fence_kiq,