[PATCH] drm/amdgpu/gfx11: properly handle regGRBM_GFX_CNTL in soft reset

[Lazar, Lijo]

On 4/8/2024 10:50 PM, Alex Deucher wrote:
> Need to take the srbm_mutex and while we are here, use the
> helper function soc21_grbm_select();
> 
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>

Thanks,
Lijo

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7a906318e4519..dc9c0f67607b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4506,14 +4506,11 @@ static int gfx_v11_0_soft_reset(void *handle)
>  
>  	gfx_v11_0_set_safe_mode(adev, 0);
>  
> +	mutex_lock(&adev->srbm_mutex);
>  	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
>  		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
>  			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
> -				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
> -				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
> +				soc21_grbm_select(adev, i, k, j, 0);
>  
>  				WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
>  				WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
> @@ -4523,16 +4520,14 @@ static int gfx_v11_0_soft_reset(void *handle)
>  	for (i = 0; i < adev->gfx.me.num_me; ++i) {
>  		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
>  			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
> -				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
> -				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
> -				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
> +				soc21_grbm_select(adev, i, k, j, 0);
>  
>  				WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
>  			}
>  		}
>  	}
> +	soc21_grbm_select(adev, 0, 0, 0, 0);
> +	mutex_unlock(&adev->srbm_mutex);
>  
>  	/* Try to acquire the gfx mutex before access to CP_VMID_RESET */
>  	r = gfx_v11_0_request_gfx_index_mutex(adev, 1);