[PATCH] drm/amdgpu/sdma5.2: use legacy HDP flush for SDMA2/3

[Christian König]

Am 20.04.24 um 21:02 schrieb Alex Deucher:
> This avoids a potential conflict with firmwares with the newer
> HDP flush mechanism.

The patch is fine, but I'm starting to wonder why we are using the newer 
HDP flush mechanism in the first place?

>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2156
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 26 +++++++++++++++-----------
>   1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index b2417ba4759b..c44ec41f1cb6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -280,17 +280,21 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   	u32 ref_and_mask = 0;
>   	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
>   
> -	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
> -
> -	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
> -			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
> -			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
> -	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
> -	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
> -	amdgpu_ring_write(ring, ref_and_mask); /* reference */
> -	amdgpu_ring_write(ring, ref_and_mask); /* mask */
> -	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
> -			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
> +	if (ring->me > 1) {
> +		amdgpu_asic_flush_hdp(adev, ring);
> +	} else {
> +		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
> +
> +		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
> +				  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
> +				  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
> +		amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
> +		amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
> +		amdgpu_ring_write(ring, ref_and_mask); /* reference */
> +		amdgpu_ring_write(ring, ref_and_mask); /* mask */
> +		amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
> +				  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
> +	}
>   }
>   
>   /**