[PATCH 24/37] drm/amd/display: Force flush after write to IPS driver signals

Aurabindo Pillai aurabindo.pillai at amd.com
Mon Apr 22 15:27:33 UTC 2024


From: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>

[Why]
It's possible that the write hasn't fully completed by the time we
send (and flush) a command to DMCUB to notify idle to request IPS2
exit.

[How]
Perform a readback of the volatile structure into dc_dmub_srv state.

Reviewed-by: Charlene Liu <charlene.liu at amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai at amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 ++
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 3177000335b2..33d3307f5c1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1296,6 +1296,7 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
 		}
 
 		ips_driver->signals = new_signals;
+		dc_dmub_srv->driver_signals = ips_driver->signals;
 	}
 
 	DC_LOG_IPS(
@@ -1339,6 +1340,7 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 		ips2_exit_count = ips_fw->ips2_exit_count;
 
 		ips_driver->signals.all = 0;
+		dc_dmub_srv->driver_signals = ips_driver->signals;
 
 		DC_LOG_IPS(
 			"%s (allow ips1=%d ips2=%d) (commit ips1=%d ips2=%d) (count rcg=%d ips1=%d ips2=%d)",
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 72cc483e1556..3297c5b33265 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -53,6 +53,7 @@ struct dc_dmub_srv {
 	void *dm;
 
 	int32_t idle_exit_counter;
+	union dmub_shared_state_ips_driver_signals driver_signals;
 	bool idle_allowed;
 	bool needs_idle_wake;
 };
-- 
2.44.0



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