[PATCH] drm/amd/display: use mpcc_count to log MPC state

[Rodrigo Siqueira Jordao]

On 4/12/24 10:39 AM, Melissa Wen wrote:
> According to [1]:
> ```
> DTN only logs 'pipe_count' instances of MPCC. However in some cases
> there are different number of MPCC than DPP (pipe_count).
> ```
> 
> As DTN log still relies on pipe_count to print mpcc state, switch to
> mpcc_count in all occurrences.
> 
> [1] https://lore.kernel.org/amd-gfx/20240328195047.2843715-39-Roman.Li@amd.com/
> 
> Signed-off-by: Melissa Wen <mwen at igalia.com>
> ---
>   drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
>   drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
>   drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
>   3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
> index 3940f25f7d9f..088224571029 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
> @@ -367,7 +367,7 @@ static void dcn10_log_color_state(struct dc *dc,
>   		 dc->caps.color.dpp.ocsc);
>   
>   	DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
> -	for (i = 0; i < pool->pipe_count; i++) {
> +	for (i = 0; i < pool->mpcc_count; i++) {
>   		struct mpcc_state s = {0};
>   
>   		pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
> index 87b43cb50c1e..a38333152654 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
> @@ -155,7 +155,7 @@ void dcn20_log_color_state(struct dc *dc,
>   	DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE"
>   		 "  OGAM mode\n");
>   
> -	for (i = 0; i < pool->pipe_count; i++) {
> +	for (i = 0; i < pool->mpcc_count; i++) {
>   		struct mpcc_state s = {0};
>   
>   		pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> index 40391dd16944..ed9141a67db3 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
> @@ -166,7 +166,7 @@ void dcn30_log_color_state(struct dc *dc,
>   		 "C21        C22        C23        C24        "
>   		 "C31        C32        C33        C34        \n");
>   
> -	for (i = 0; i < pool->pipe_count; i++) {
> +	for (i = 0; i < pool->mpcc_count; i++) {
>   		struct mpcc_state s = {0};
>   
>   		pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

Hi Melissa,

Thanks a lot for your patch.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>

I already merged this change to asdn.

Thanks
Siqueira