[PATCH] drm/amd/pm: fix uninitialized variable warning for smu_v13
Tim Huang
Tim.Huang at amd.com
Mon Apr 29 07:41:36 UTC 2024
Clear warning that using uninitialized variable when the dpm is
not enabled and reuse the code for SMU13 to get the boot frequency.
Signed-off-by: Tim Huang <Tim.Huang at amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 4 ++
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 55 +++++++++++++------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 28 +---------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 28 +---------
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 28 +---------
5 files changed, 51 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index d9700a3f28d2..e58220a7ee2f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -298,5 +298,9 @@ int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);
int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
struct freq_band_range *exclusion_ranges);
+
+int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a8d34adc7d3f..ed5a7a83c9e2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1559,22 +1559,9 @@ int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
uint32_t clock_limit;
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
+ ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
+ if (ret)
+ return ret;
/* clock in Mhz unit */
if (min)
@@ -1894,6 +1881,40 @@ int smu_v13_0_set_power_source(struct smu_context *smu,
NULL);
}
+int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+{
+ int ret = 0;
+
+ switch (clk_type) {
+ case SMU_MCLK:
+ case SMU_UCLK:
+ *value = smu->smu_table.boot_values.uclk;
+ break;
+ case SMU_FCLK:
+ *value = smu->smu_table.boot_values.fclk;
+ break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ *value = smu->smu_table.boot_values.gfxclk;
+ break;
+ case SMU_SOCCLK:
+ *value = smu->smu_table.boot_values.socclk;
+ break;
+ case SMU_VCLK:
+ *value = smu->smu_table.boot_values.vclk;
+ break;
+ case SMU_DCLK:
+ *value = smu->smu_table.boot_values.dclk;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type, uint16_t level,
uint32_t *value)
@@ -1905,7 +1926,7 @@ int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
return -EINVAL;
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
- return 0;
+ return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
clk_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_CLK,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 88f1a0d878f3..e283b282ec27 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -756,31 +756,9 @@ static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
int ret = 0;
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_FCLK:
- clock_limit = smu->smu_table.boot_values.fclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- case SMU_VCLK:
- clock_limit = smu->smu_table.boot_values.vclk;
- break;
- case SMU_DCLK:
- clock_limit = smu->smu_table.boot_values.dclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
+ ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
+ if (ret)
+ return ret;
/* clock in Mhz unit */
if (min)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 218f209c3775..59854465d711 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -733,31 +733,9 @@ static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
int ret = 0;
if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_FCLK:
- clock_limit = smu->smu_table.boot_values.fclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- case SMU_VCLK:
- clock_limit = smu->smu_table.boot_values.vclk;
- break;
- case SMU_DCLK:
- clock_limit = smu->smu_table.boot_values.dclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
+ ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
+ if (ret)
+ return ret;
/* clock in Mhz unit */
if (min)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index d8bcf765a803..5917c88cc87d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -867,31 +867,9 @@ static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_FCLK:
- clock_limit = smu->smu_table.boot_values.fclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- case SMU_VCLK:
- clock_limit = smu->smu_table.boot_values.vclk;
- break;
- case SMU_DCLK:
- clock_limit = smu->smu_table.boot_values.dclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
+ ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
+ if (ret)
+ return ret;
/* clock in Mhz unit */
if (min)
--
2.39.2
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