[PATCH 07/11] drm/amdgpu/mes12: add legacy setting hw resource interface

[Alex Deucher]

From: Jack Xiao <Jack.Xiao at amd.com>

For unified mes fw, add the legacy interface to set hardware
resources.

v2: remove warning (Alex)

Signed-off-by: Jack Xiao <Jack.Xiao at amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v12_0.c        | 22 +++++++++++++++++--
 drivers/gpu/drm/amd/include/mes_v12_api_def.h | 22 +++++++++++++++++++
 2 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index cf6dea13cc955..0b67ff9c04924 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -376,6 +376,22 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
 			offsetof(union MESAPI__MISC, api_status));
 }
 
+static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes)
+{
+	union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
+
+	memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
+
+	mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
+	mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
+	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
+
+	return mes_v12_0_submit_pkt_and_poll_completion(mes,
+			&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
+			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
+}
+
 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes)
 {
 	int i;
@@ -424,7 +440,6 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes)
 	mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 	mes_set_hw_res_pkt.oversubscription_timer = 50;
 
-
 	mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
 	mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
 
@@ -1043,7 +1058,7 @@ static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
 	ring = &adev->gfx.kiq[0].ring;
 
 	ring->me = 3;
-	ring->pipe = 1;
+	ring->pipe = adev->enable_uni_mes ? 0 : 1;
 	ring->queue = 0;
 
 	ring->adev = NULL;
@@ -1309,6 +1324,9 @@ static int mes_v12_0_hw_init(void *handle)
 	if (r)
 		goto failure;
 
+	if (adev->enable_uni_mes)
+		mes_v12_0_set_hw_resources_1(&adev->mes);
+
 	mes_v12_0_init_aggregated_doorbell(&adev->mes);
 
 	/* Enable the MES to handle doorbell ring on unmapped queue */
diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
index 81cc0a5540492..e3211daa9c2e4 100644
--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
@@ -62,6 +62,7 @@ enum MES_SCH_API_OPCODE {
 	MES_SCH_API_AMD_LOG			= 16,
 	MES_SCH_API_SET_SE_MODE			= 17,
 	MES_SCH_API_SET_GANG_SUBMIT		= 18,
+	MES_SCH_API_SET_HW_RSRC_1               = 19,
 
 	MES_SCH_API_MAX = 0xFF
 };
@@ -252,6 +253,27 @@ union MESAPI_SET_HW_RESOURCES {
 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 };
 
+union MESAPI_SET_HW_RESOURCES_1 {
+	struct {
+		union MES_API_HEADER                header;
+		struct MES_API_STATUS               api_status;
+		uint64_t                            timestamp;
+		union {
+			struct {
+				uint32_t enable_mes_debug_ctx : 1;
+				uint32_t reserved : 31;
+			};
+			uint32_t uint32_all;
+		};
+		uint64_t                            mes_debug_ctx_mc_addr;
+		uint32_t                            mes_debug_ctx_size;
+		/* unit is 100ms */
+		uint32_t                            mes_kiq_unmap_timeout;
+	};
+
+	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
 union MESAPI__ADD_QUEUE {
 	struct {
 		union MES_API_HEADER	header;
-- 
2.44.0