[PATCH] drm/amdgpu/mes: refine for maximum packet execution

[Xiao, Jack]

[Public]

The maximum sched_hw_submission value will be set to 8. The value will result that the maximum number of packet execution which is not greater than firmware allowed.

Regards,
Jack

-----Original Message-----
From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Tuesday, August 6, 2024 10:34 PM
To: Xiao, Jack <Jack.Xiao at amd.com>; amd-gfx at lists.freedesktop.org; ckoenig.leichtzumerken at gmail.com
Subject: RE: [PATCH] drm/amdgpu/mes: refine for maximum packet execution

[Public]

> -----Original Message-----
> From: Xiao, Jack <Jack.Xiao at amd.com>
> Sent: Tuesday, July 23, 2024 4:28 AM
> To: amd-gfx at lists.freedesktop.org; Deucher, Alexander
> <Alexander.Deucher at amd.com>; ckoenig.leichtzumerken at gmail.com
> Cc: Xiao, Jack <Jack.Xiao at amd.com>
> Subject: [PATCH] drm/amdgpu/mes: refine for maximum packet execution
>
> Only allow API_NUMBER_OF_COMMAND_MAX packet in mes ring buffer, refine
> the code for maximum packet execution.
>
> Signed-off-by: Jack Xiao <Jack.Xiao at amd.com>

Any updates on this patch?

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 ++
>  drivers/gpu/drm/amd/amdgpu/mes_v11_0.c   | 2 +-
>  drivers/gpu/drm/amd/amdgpu/mes_v12_0.c   | 2 +-
>  3 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index ad49cecb20b8..dfe487521a4a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -212,6 +212,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ring *ring,
>        */
>       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
>               sched_hw_submission = max(sched_hw_submission, 256);
> +     else if (ring->funcs->type == AMDGPU_RING_TYPE_MES)
> +             sched_hw_submission = 32;
>       else if (ring == &adev->sdma.instance[0].page)
>               sched_hw_submission = 256;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 68c74adf79f1..951f13e01ee9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -198,7 +198,7 @@ static int
> mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
>
>       seq = ++ring->fence_drv.sync_seq;
>       r = amdgpu_fence_wait_polling(ring,
> -                                   seq - ring->fence_drv.num_fences_mask,
> +                                   seq -
> (API_NUMBER_OF_COMMAND_MAX/2 - 1),
>                                     timeout);
>       if (r < 1)
>               goto error_undo;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> index 48e01206bcc4..dc65f28d1795 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> @@ -184,7 +184,7 @@ static int
> mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
>
>       seq = ++ring->fence_drv.sync_seq;
>       r = amdgpu_fence_wait_polling(ring,
> -                                   seq - ring->fence_drv.num_fences_mask,
> +                                   seq -
> (API_NUMBER_OF_COMMAND_MAX/2 - 1),
>                                     timeout);
>       if (r < 1)
>               goto error_undo;
> --
> 2.41.0