amd-gfx Digest, Vol 98, Issue 216

Prosyak, Vitaly Vitaly.Prosyak at amd.com
Thu Aug 8 17:00:36 UTC 2024


[AMD Official Use Only - AMD Internal Distribution Only]

Acked-by: Vitaly Prosyak <vitaly.prosyak at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of amd-gfx-request at lists.freedesktop.org <amd-gfx-request at lists.freedesktop.org>
Sent: Wednesday, July 17, 2024 4:39 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Subject: amd-gfx Digest, Vol 98, Issue 216

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Today's Topics:

   1. [PATCH 2/4] drm/amdgpu/gfx11: properly handle error ints on
      all pipes (Alex Deucher)
   2. [PATCH 4/4] drm/amdgpu/gfx9: properly handle error ints on
      all pipes (Alex Deucher)
   3. [PATCH 3/4] drm/amdgpu/gfx12: properly handle error ints on
      all pipes (Alex Deucher)


----------------------------------------------------------------------

Message: 1
Date: Wed, 17 Jul 2024 16:38:45 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher at amd.com>
Subject: [PATCH 2/4] drm/amdgpu/gfx11: properly handle error ints on
        all pipes
Message-ID: <20240717203847.14600-2-alexander.deucher at amd.com>
Content-Type: text/plain

Need to handle the interrupt enables for all pipes.

v2: fix indexing (Jessie)

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 134 ++++++++++++++++++++-----
 1 file changed, 111 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 554aae995f41..02efa475eb7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1953,26 +1953,74 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
         gfx_v11_0_init_gds_vmid(adev);
 }

+static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev,
+                                     int me, int pipe)
+{
+       if (me != 0)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
+       case 1:
+               return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
+       default:
+               return 0;
+       }
+}
+
+static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                     int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
+       case 2:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
+       case 3:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
                                                bool enable)
 {
-       u32 tmp;
+       u32 tmp, cp_int_cntl_reg;
+       int i, j;

         if (amdgpu_sriov_vf(adev))
                 return;

-       tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
-
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
-                           enable ? 1 : 0);
-
-       WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
+       for (i = 0; i < adev->gfx.me.num_me; i++) {
+               for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                       cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
+
+                       if (cp_int_cntl_reg) {
+                               tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
+                       }
+               }
+       }
 }

 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
@@ -6201,15 +6249,42 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,

 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                               struct amdgpu_irq_src *source,
-                                             unsigned type,
+                                             unsigned int type,
                                               enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
-               WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
-                              PRIV_REG_INT_ENABLE,
-                              state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                 break;
         default:
                 break;
@@ -6220,15 +6295,28 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,

 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
                                                struct amdgpu_irq_src *source,
-                                              unsigned type,
+                                              unsigned int type,
                                                enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
-               WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
-                              PRIV_INSTR_INT_ENABLE,
-                              state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   PRIV_INSTR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                 break;
         default:
                 break;
@@ -6252,8 +6340,8 @@ static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
         case 0:
                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                         ring = &adev->gfx.gfx_ring[i];
-                       /* we only enabled 1 gfx queue per pipe for now */
-                       if (ring->me == me_id && ring->pipe == pipe_id)
+                       if (ring->me == me_id && ring->pipe == pipe_id &&
+                           ring->queue == queue_id)
                                 drm_sched_fault(&ring->sched);
                 }
                 break;
--
2.45.2



------------------------------

Message: 2
Date: Wed, 17 Jul 2024 16:38:47 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher at amd.com>
Subject: [PATCH 4/4] drm/amdgpu/gfx9: properly handle error ints on
        all pipes
Message-ID: <20240717203847.14600-4-alexander.deucher at amd.com>
Content-Type: text/plain

Need to handle the interrupt enables for all pipes.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 44 +++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 50 +++++++++++++++++++++++--
 2 files changed, 89 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d4e38edc9353..97476fb2ca40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2634,7 +2634,7 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
-       if(adev->gfx.num_gfx_rings)
+       if (adev->gfx.num_gfx_rings)
                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
@@ -5929,17 +5929,59 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
         }
 }

+static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                    int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
+       case 2:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
+       case 3:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              unsigned type,
                                              enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
                                PRIV_REG_INT_ENABLE,
                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                 break;
         default:
                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 2ac398184e12..43a3ef276b5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2899,21 +2899,63 @@ static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
         }
 }

+static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                    int xcc_id, int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
+       case 2:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
+       case 3:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                              struct amdgpu_irq_src *source,
                                              unsigned type,
                                              enum amdgpu_interrupt_state state)
 {
-       int i, num_xcc;
+       u32 mec_int_cntl_reg, mec_int_cntl;
+       int i, j, k, num_xcc;

         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
-               for (i = 0; i < num_xcc; i++)
+               for (i = 0; i < num_xcc; i++) {
                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
-                               PRIV_REG_INT_ENABLE,
-                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                             PRIV_REG_INT_ENABLE,
+                                             state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                       for (j = 0; j < adev->gfx.mec.num_mec; j++) {
+                               for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
+                                       /* MECs start at 1 */
+                                       mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
+
+                                       if (mec_int_cntl_reg) {
+                                               mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);
+                                               mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                            PRIV_REG_INT_ENABLE,
+                                                                            state == AMDGPU_IRQ_STATE_ENABLE ?
+                                                                            1 : 0);
+                                               WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);
+                                       }
+                               }
+                       }
+               }
                 break;
         default:
                 break;
--
2.45.2



------------------------------

Message: 3
Date: Wed, 17 Jul 2024 16:38:46 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher at amd.com>
Subject: [PATCH 3/4] drm/amdgpu/gfx12: properly handle error ints on
        all pipes
Message-ID: <20240717203847.14600-3-alexander.deucher at amd.com>
Content-Type: text/plain

Need to handle the interrupt enables for all pipes.

v2: fix indexing (Jessie)

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 130 ++++++++++++++++++++-----
 1 file changed, 106 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 567f9196d6a0..c74c8a60a23a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1680,26 +1680,68 @@ static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
         gfx_v12_0_init_compute_vmid(adev);
 }

+static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
+                                     int me, int pipe)
+{
+       if (me != 0)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
+       default:
+               return 0;
+       }
+}
+
+static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                     int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
-                                               bool enable)
+                                              bool enable)
 {
-       u32 tmp;
+       u32 tmp, cp_int_cntl_reg;
+       int i, j;

         if (amdgpu_sriov_vf(adev))
                 return;

-       tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
-
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
-                           enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
-                           enable ? 1 : 0);
-
-       WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
+       for (i = 0; i < adev->gfx.me.num_me; i++) {
+               for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                       cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
+
+                       if (cp_int_cntl_reg) {
+                               tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
+                                                   enable ? 1 : 0);
+                               WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
+                       }
+               }
+       }
 }

 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
@@ -4745,15 +4787,42 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,

 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                               struct amdgpu_irq_src *source,
-                                             unsigned type,
+                                             unsigned int type,
                                               enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
-               WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
-                                     PRIV_REG_INT_ENABLE,
-                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                 break;
         default:
                 break;
@@ -4764,15 +4833,28 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,

 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
                                                struct amdgpu_irq_src *source,
-                                              unsigned type,
+                                              unsigned int type,
                                                enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
         case AMDGPU_IRQ_STATE_ENABLE:
-               WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
-                              PRIV_INSTR_INT_ENABLE,
-                              state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   PRIV_INSTR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                 break;
         default:
                 break;
@@ -4796,8 +4878,8 @@ static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
         case 0:
                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                         ring = &adev->gfx.gfx_ring[i];
-                       /* we only enabled 1 gfx queue per pipe for now */
-                       if (ring->me == me_id && ring->pipe == pipe_id)
+                       if (ring->me == me_id && ring->pipe == pipe_id &&
+                           ring->queue == queue_id)
                                 drm_sched_fault(&ring->sched);
                 }
                 break;
--
2.45.2



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