amd-gfx Digest, Vol 98, Issue 218

Prosyak, Vitaly Vitaly.Prosyak at amd.com
Thu Aug 8 17:03:08 UTC 2024


[AMD Official Use Only - AMD Internal Distribution Only]

Acked-by: Vitaly Prosyak <vitaly.prosyak at amd.com>
The entire series of patches for gfx 7, 8, 9, 11 and compute gfx 10, 12
 for queue_reset was tested using the new IGT test, amd_queue_reset, which has been merged upstream.
________________________________
From: Prosyak, Vitaly <Vitaly.Prosyak at amd.com>
Sent: Thursday, August 8, 2024 1:01 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: Re: amd-gfx Digest, Vol 98, Issue 218

Acked-by: Vitaly Prosyak <vitaly.prosyak at amd.com>
The entire series of patches for gfx 7, 8, 9, 11 and compute gfx 10, 12
 for queue_reset was tested using the new IGT test, amd_queue_reset, which has been merged upstream.
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of amd-gfx-request at lists.freedesktop.org <amd-gfx-request at lists.freedesktop.org>
Sent: Wednesday, July 17, 2024 4:40 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Subject: amd-gfx Digest, Vol 98, Issue 218

Send amd-gfx mailing list submissions to
        amd-gfx at lists.freedesktop.org

To subscribe or unsubscribe via the World Wide Web, visit
        https://lists.freedesktop.org/mailman/listinfo/amd-gfx
or, via email, send a message with subject or body 'help' to
        amd-gfx-request at lists.freedesktop.org

You can reach the person managing the list at
        amd-gfx-owner at lists.freedesktop.org

When replying, please edit your Subject line so it is more specific
than "Re: Contents of amd-gfx digest..."


Today's Topics:

   1. [PATCH 6/6] drm/amdgpu/gfx9.4.3: Enable bad opcode interrupt
      (Alex Deucher)
   2. [PATCH 2/6] drm/amdgpu/gfx11: Enable bad opcode interrupt
      (Alex Deucher)
   3. [PATCH 4/6] drm/amdgpu/gfx12: Enable bad opcode interrupt
      (Alex Deucher)


----------------------------------------------------------------------

Message: 1
Date: Wed, 17 Jul 2024 16:40:11 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher at amd.com>
Subject: [PATCH 6/6] drm/amdgpu/gfx9.4.3: Enable bad opcode interrupt
Message-ID: <20240717204011.15342-6-alexander.deucher at amd.com>
Content-Type: text/plain

For the bad opcode case, it will cause CP/ME hang.
The firmware will prevent the ME side from hanging by raising a bad opcode interrupt.
And the driver needs to perform a vmid reset when receiving the interrupt.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 69 +++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 43a3ef276b5f..98fe6c40da64 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -901,6 +901,13 @@ static int gfx_v9_4_3_sw_init(void *handle)
         if (r)
                 return r;

+       /* Bad opcode Event */
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
+                             GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR,
+                             &adev->gfx.bad_op_irq);
+       if (r)
+               return r;
+
         /* Privileged reg */
         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
                               &adev->gfx.priv_reg_irq);
@@ -2162,6 +2169,7 @@ static int gfx_v9_4_3_hw_fini(void *handle)

         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+       amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);

         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
         for (i = 0; i < num_xcc; i++) {
@@ -2327,6 +2335,10 @@ static int gfx_v9_4_3_late_init(void *handle)
         if (r)
                 return r;

+       r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
+       if (r)
+               return r;
+
         if (adev->gfx.ras &&
             adev->gfx.ras->enable_watchdog_timer)
                 adev->gfx.ras->enable_watchdog_timer(adev);
@@ -2964,6 +2976,46 @@ static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev,
+                                            struct amdgpu_irq_src *source,
+                                            unsigned type,
+                                            enum amdgpu_interrupt_state state)
+{
+       u32 mec_int_cntl_reg, mec_int_cntl;
+       int i, j, k, num_xcc;
+
+       num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+       switch (state) {
+       case AMDGPU_IRQ_STATE_DISABLE:
+       case AMDGPU_IRQ_STATE_ENABLE:
+               for (i = 0; i < num_xcc; i++) {
+                       WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
+                                             OPCODE_ERROR_INT_ENABLE,
+                                             state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                       for (j = 0; j < adev->gfx.mec.num_mec; j++) {
+                               for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
+                                       /* MECs start at 1 */
+                                       mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
+
+                                       if (mec_int_cntl_reg) {
+                                               mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);
+                                               mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                            OPCODE_ERROR_INT_ENABLE,
+                                                                            state == AMDGPU_IRQ_STATE_ENABLE ?
+                                                                            1 : 0);
+                                               WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);
+                                       }
+                               }
+                       }
+               }
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
                                               struct amdgpu_irq_src *source,
                                               unsigned type,
@@ -3116,6 +3168,15 @@ static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev,
+                                struct amdgpu_irq_src *source,
+                                struct amdgpu_iv_entry *entry)
+{
+       DRM_ERROR("Illegal opcode in command stream\n");
+       gfx_v9_4_3_fault(adev, entry);
+       return 0;
+}
+
 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
                                   struct amdgpu_irq_src *source,
                                   struct amdgpu_iv_entry *entry)
@@ -4228,6 +4289,11 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
         .process = gfx_v9_4_3_priv_reg_irq,
 };

+static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = {
+       .set = gfx_v9_4_3_set_bad_op_fault_state,
+       .process = gfx_v9_4_3_bad_op_irq,
+};
+
 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
         .set = gfx_v9_4_3_set_priv_inst_fault_state,
         .process = gfx_v9_4_3_priv_inst_irq,
@@ -4241,6 +4307,9 @@ static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
         adev->gfx.priv_reg_irq.num_types = 1;
         adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;

+       adev->gfx.bad_op_irq.num_types = 1;
+       adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs;
+
         adev->gfx.priv_inst_irq.num_types = 1;
         adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
 }
--
2.45.2



------------------------------

Message: 2
Date: Wed, 17 Jul 2024 16:40:07 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Jesse Zhang <jesse.zhang at amd.com>, Jesse Zhang
        <Jesse.Zhang at amd.com>, Prike Liang <Prike.Liang at amd.com>, Alex Deucher
        <alexander.deucher at amd.com>
Subject: [PATCH 2/6] drm/amdgpu/gfx11: Enable bad opcode interrupt
Message-ID: <20240717204011.15342-2-alexander.deucher at amd.com>
Content-Type: text/plain

From: Jesse Zhang <jesse.zhang at amd.com>

For the bad opcode case, it will cause CP/ME hang.
The firmware will prevent the ME side from hanging by raising a bad opcode interrupt.
And the driver needs to perform a vmid reset when receiving the interrupt.

v2: update irq naming (drop priv) (Alex)

Signed-off-by: Jesse Zhang <Jesse.Zhang at amd.com>
Reviewed-by: Prike Liang <Prike.Liang at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 73 ++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 02efa475eb7e..ce5cb60b8628 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1569,6 +1569,13 @@ static int gfx_v11_0_sw_init(void *handle)
         if (r)
                 return r;

+       /* Bad opcode Event */
+       r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
+                             GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR,
+                             &adev->gfx.bad_op_irq);
+       if (r)
+               return r;
+
         /* Privileged reg */
         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
@@ -4646,6 +4653,7 @@ static int gfx_v11_0_hw_fini(void *handle)

         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+       amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);

         if (!adev->no_hw_access) {
                 if (amdgpu_async_gfx_ring) {
@@ -5002,6 +5010,9 @@ static int gfx_v11_0_late_init(void *handle)
         if (r)
                 return r;

+       r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
+       if (r)
+               return r;
         return 0;
 }

@@ -6293,6 +6304,51 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev,
+                                           struct amdgpu_irq_src *source,
+                                           unsigned type,
+                                           enum amdgpu_interrupt_state state)
+{
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i , j;
+
+       switch (state) {
+       case AMDGPU_IRQ_STATE_DISABLE:
+       case AMDGPU_IRQ_STATE_ENABLE:
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   OPCODE_ERROR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   OPCODE_ERROR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
+
 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
                                                struct amdgpu_irq_src *source,
                                                unsigned int type,
@@ -6369,6 +6425,15 @@ static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev,
+                               struct amdgpu_irq_src *source,
+                               struct amdgpu_iv_entry *entry)
+{
+       DRM_ERROR("Illegal opcode in command stream \n");
+       gfx_v11_0_handle_priv_fault(adev, entry);
+       return 0;
+}
+
 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
                                    struct amdgpu_irq_src *source,
                                    struct amdgpu_iv_entry *entry)
@@ -6747,6 +6812,11 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
         .process = gfx_v11_0_priv_reg_irq,
 };

+static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = {
+       .set = gfx_v11_0_set_bad_op_fault_state,
+       .process = gfx_v11_0_bad_op_irq,
+};
+
 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
         .set = gfx_v11_0_set_priv_inst_fault_state,
         .process = gfx_v11_0_priv_inst_irq,
@@ -6764,6 +6834,9 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
         adev->gfx.priv_reg_irq.num_types = 1;
         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;

+       adev->gfx.bad_op_irq.num_types = 1;
+       adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs;
+
         adev->gfx.priv_inst_irq.num_types = 1;
         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;

--
2.45.2



------------------------------

Message: 3
Date: Wed, 17 Jul 2024 16:40:09 -0400
From: Alex Deucher <alexander.deucher at amd.com>
To: <amd-gfx at lists.freedesktop.org>
Cc: Jesse Zhang <jesse.zhang at amd.com>, Alex Deucher
        <alexander.deucher at amd.com>
Subject: [PATCH 4/6] drm/amdgpu/gfx12: Enable bad opcode interrupt
Message-ID: <20240717204011.15342-4-alexander.deucher at amd.com>
Content-Type: text/plain

From: Jesse Zhang <jesse.zhang at amd.com>

For the bad opcode case, it will cause CP/ME hang.
The firmware will prevent the ME side from hanging by raising a bad opcode interrupt.
And the driver needs to perform a vmid reset when receiving the interrupt.

v2: update irq naming (drop priv) (Alex)

Signed-off-by: Jesse Zhang <jesse.zhang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 74 ++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index c74c8a60a23a..63b073fd4dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1349,6 +1349,13 @@ static int gfx_v12_0_sw_init(void *handle)
         if (r)
                 return r;

+       /* Bad opcode Event */
+       r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
+                             GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR,
+                             &adev->gfx.bad_op_irq);
+       if (r)
+               return r;
+
         /* Privileged reg */
         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
@@ -3592,6 +3599,7 @@ static int gfx_v12_0_hw_fini(void *handle)

         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+       amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);

         if (!adev->no_hw_access) {
                 if (amdgpu_async_gfx_ring) {
@@ -3712,6 +3720,10 @@ static int gfx_v12_0_late_init(void *handle)
         if (r)
                 return r;

+       r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
+       if (r)
+               return r;
+
         return 0;
 }

@@ -4831,6 +4843,51 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
+                                           struct amdgpu_irq_src *source,
+                                           unsigned type,
+                                           enum amdgpu_interrupt_state state)
+{
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i , j;
+
+       switch (state) {
+       case AMDGPU_IRQ_STATE_DISABLE:
+       case AMDGPU_IRQ_STATE_ENABLE:
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+                               cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+                                                                   OPCODE_ERROR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   OPCODE_ERROR_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
+
 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
                                                struct amdgpu_irq_src *source,
                                                unsigned int type,
@@ -4907,6 +4964,15 @@ static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
         return 0;
 }

+static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
+                               struct amdgpu_irq_src *source,
+                               struct amdgpu_iv_entry *entry)
+{
+       DRM_ERROR("Illegal opcode in command stream \n");
+       gfx_v12_0_handle_priv_fault(adev, entry);
+       return 0;
+}
+
 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
                                    struct amdgpu_irq_src *source,
                                    struct amdgpu_iv_entry *entry)
@@ -5219,6 +5285,11 @@ static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
         .process = gfx_v12_0_priv_reg_irq,
 };

+static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
+       .set = gfx_v12_0_set_bad_op_fault_state,
+       .process = gfx_v12_0_bad_op_irq,
+};
+
 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
         .set = gfx_v12_0_set_priv_inst_fault_state,
         .process = gfx_v12_0_priv_inst_irq,
@@ -5232,6 +5303,9 @@ static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
         adev->gfx.priv_reg_irq.num_types = 1;
         adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;

+       adev->gfx.bad_op_irq.num_types = 1;
+       adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
+
         adev->gfx.priv_inst_irq.num_types = 1;
         adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
 }
--
2.45.2



------------------------------

Subject: Digest Footer

_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


------------------------------

End of amd-gfx Digest, Vol 98, Issue 218
****************************************
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20240808/431eb159/attachment-0001.htm>


More information about the amd-gfx mailing list