amd-gfx Digest, Vol 98, Issue 341
Prosyak, Vitaly
Vitaly.Prosyak at amd.com
Thu Aug 8 21:36:02 UTC 2024
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Vitaly Prosyak <vitaly.prosyak at amd.com>
The entire series of patches [0-53 ] for gfx 7, 8, 9, 11 and compute gfx 10, 12
queue/pipe reset was tested using the new IGT test, amd_queue_reset, which has been merged upstream.
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of amd-gfx-request at lists.freedesktop.org <amd-gfx-request at lists.freedesktop.org>
Sent: Thursday, July 25, 2024 12:35 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Subject: amd-gfx Digest, Vol 98, Issue 341
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Today's Topics:
1. Re: [PATCH V2 00/53] GC per queue reset (Alex Deucher)
2. Re: [PATCH v4 01/11] drm/amd/display: clean unused variables
for hdmi freesync parser (Alex Hung)
3. Re: [PATCH 1/2] drm/sched: Add error code parameter to
drm_sched_start (Alex Deucher)
4. Re: [PATCH v4 02/11] drm/amd/display: switch
amdgpu_dm_connector to use struct drm_edid (Alex Hung)
----------------------------------------------------------------------
Message: 1
Date: Thu, 25 Jul 2024 11:29:14 -0400
From: Alex Deucher <alexdeucher at gmail.com>
To: Alex Deucher <alexander.deucher at amd.com>
Cc: amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH V2 00/53] GC per queue reset
Message-ID:
<CADnq5_NWdzoTVOuCEOFMhC0GF+26=2z8nknADXyiLxmAs9fTzQ at mail.gmail.com>
Content-Type: text/plain; charset="UTF-8"
On Thu, Jul 25, 2024 at 11:20?AM Alex Deucher <alexander.deucher at amd.com> wrote:
>
> This adds preliminary support for GC per queue reset. In this
> case, only the jobs currently in the queue are lost. If this
> fails, we fall back to a full adapter reset.
>
> V2: Fix fallbacks to full adapter reset
> RLC safemode cleanup
> Preliminary support for older GPUs
Forgot to add a git link as well:
https://gitlab.freedesktop.org/agd5f/linux/-/tree/amd-staging-drm-next-queue-reset?ref_type=heads
Alex
>
> Alex Deucher (38):
> drm/amdgpu/gfx10: handle SDMA in KIQ map/unmap
> drm/amdgpu/mes11: handle second gfx pipe
> drm/amdgpu/mes: add API for legacy queue reset
> drm/amdgpu/mes11: add API for legacy queue reset
> drm/amdgpu/mes12: add API for legacy queue reset
> drm/amdgpu/mes: add API for user queue reset
> drm/amdgpu/mes11: add API for user queue reset
> drm/amdgpu/mes12: add API for user queue reset
> drm/amdgpu: add new ring reset callback
> drm/amdgpu: add per ring reset support (v5)
> drm/amdgpu/gfx11: add ring reset callbacks
> drm/amdgpu/gfx11: rename gfx_v11_0_gfx_init_queue()
> drm/amdgpu/gfx10: add ring reset callbacks
> drm/amdgpu/gfx10: rework reset sequence
> drm/amdgpu/gfx9: add ring reset callback
> drm/amdgpu/gfx9.4.3: add ring reset callback
> drm/amdgpu/gfx12: add ring reset callbacks
> drm/amdgpu/gfx12: fallback to driver reset compute queue directly
> drm/amdgpu/gfx11: enter safe mode before touching CP_INT_CNTL
> drm/amdgpu/gfx11: add a mutex for the gfx semaphore
> drm/amdgpu/gfx11: export gfx_v11_0_request_gfx_index_mutex()
> drm/amdgpu/gfx9: per queue reset only on bare metal
> drm/amdgpu/gfx10: per queue reset only on bare metal
> drm/amdgpu/gfx11: per queue reset only on bare metal
> drm/amdgpu/gfx12: per queue reset only on bare metal
> drm/amdgpu/gfx9: add ring reset callback for gfx
> drm/amdgpu/gfx8: add ring reset callback for gfx
> drm/amdgpu/gfx7: add ring reset callback for gfx
> drm/amdgpu/gfx9: use proper rlc safe mode helpers
> drm/amdgpu/gfx9.4.3: use proper rlc safe mode helpers
> drm/amdgpu/gfx10: use proper rlc safe mode helpers
> drm/amdgpu/gfx11: use proper rlc safe mode helpers
> drm/amdgpu/gfx12: use proper rlc safe mode helpers
> drm/amdgpu/gfx12: use rlc safe mode for soft recovery
> drm/amdgpu/gfx11: use rlc safe mode for soft recovery
> drm/amdgpu/gfx10: use rlc safe mode for soft recovery
> drm/amdgpu/gfx9.4.3: use rlc safe mode for soft recovery
> drm/amdgpu/gfx9: use rlc safe mode for soft recovery
>
> Jiadong Zhu (13):
> drm/amdgpu/gfx11: wait for reset done before remap
> drm/amdgpu/gfx10: remap queue after reset successfully
> drm/amdgpu/gfx10: wait for reset done before remap
> drm/amdgpu/gfx9: remap queue after reset successfully
> drm/amdgpu/gfx9: wait for reset done before remap
> drm/amdgpu/gfx9.4.3: remap queue after reset successfully
> drm/amdgpu/gfx_9.4.3: wait for reset done before remap
> drm/amdgpu/gfx: add a new kiq_pm4_funcs callback for reset_hw_queue
> drm/amdgpu/gfx9: implement reset_hw_queue for gfx9
> drm/amdgpu/gfx9.4.3: implement reset_hw_queue for gfx9.4.3
> drm/amdgpu/mes: modify mes api for mmio queue reset
> drm/amdgpu/mes: implement amdgpu_mes_reset_hw_queue_mmio
> drm/amdgpu/mes11: implement mmio queue reset for gfx11
>
> Prike Liang (2):
> drm/amdgpu: increase the reset counter for the queue reset
> drm/amdgpu/gfx11: fallback to driver reset compute queue directly (v2)
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 20 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 88 ++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 37 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +
> drivers/gpu/drm/amd/amdgpu/cikd.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 251 +++++++++++++++++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 127 +++++++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h | 3 +
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 103 ++++++++-
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 76 ++++++-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 75 +++++-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 179 ++++++++++++++-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 132 ++++++++++-
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 134 +++++++++++
> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 54 +++++
> drivers/gpu/drm/amd/amdgpu/nvd.h | 2 +
> drivers/gpu/drm/amd/amdgpu/vid.h | 1 +
> 19 files changed, 1243 insertions(+), 49 deletions(-)
>
> --
> 2.45.2
>
------------------------------
Message: 2
Date: Thu, 25 Jul 2024 10:23:36 -0600
From: Alex Hung <alex.hung at amd.com>
To: Melissa Wen <mwen at igalia.com>, harry.wentland at amd.com,
sunpeng.li at amd.com, Rodrigo.Siqueira at amd.com,
alexander.deucher at amd.com, christian.koenig at amd.com,
Xinhui.Pan at amd.com, airlied at gmail.com, daniel at ffwll.ch
Cc: Mario Limonciello <mario.limonciello at amd.com>, Jani Nikula
<jani.nikula at linux.intel.com>, amd-gfx at lists.freedesktop.org,
dri-devel at lists.freedesktop.org, kernel-dev at igalia.com
Subject: Re: [PATCH v4 01/11] drm/amd/display: clean unused variables
for hdmi freesync parser
Message-ID: <b0017268-5651-4031-901e-45e64319d537 at amd.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Hi Melissa,
There are no commit messages in this patch.
Also, do you think this can be merged with Patch 5 "drm/amd/display:
remove redundant freesync parser for DP"?
On 2024-07-05 21:35, Melissa Wen wrote:
> Signed-off-by: Melissa Wen <mwen at igalia.com>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 98cf523a629e..1dfa7ec9af35 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -12108,9 +12108,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
> if (i >= 0 && vsdb_info.freesync_supported) {
> - timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> -
> amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
> amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
> if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
------------------------------
Message: 3
Date: Thu, 25 Jul 2024 12:30:07 -0400
From: Alex Deucher <alexdeucher at gmail.com>
To: vitaly.prosyak at amd.com
Cc: amd-gfx at lists.freedesktop.org, dri-devel at lists.freedesktop.org,
alexander.deucher at amd.com, christian.koenig at amd.com,
jesse.zhang at amd.com
Subject: Re: [PATCH 1/2] drm/sched: Add error code parameter to
drm_sched_start
Message-ID:
<CADnq5_NPmHX_1j9xifr-wk3VjB5j5_inmrrP8JknQ-49A2UqwA at mail.gmail.com>
Content-Type: text/plain; charset="UTF-8"
On Wed, Jul 24, 2024 at 11:30?PM <vitaly.prosyak at amd.com> wrote:
>
> From: Vitaly Prosyak <vitaly.prosyak at amd.com>
>
> The current implementation of drm_sched_start uses a hardcoded -ECANCELED to dispose of a job when
> the parent/hw fence is NULL. This results in drm_sched_job_done being called with -ECANCELED for
> each job with a NULL parent in the pending list, making it difficult to distinguish between recovery
> methods, whether a queue reset or a full GPU reset was used.
>
> To improve this, we first try a soft recovery for timeout jobs and use the error code -ENODATA.
> If soft recovery fails, we proceed with a queue reset, where the error code remains -ENODATA for
> the job. Finally, for a full GPU reset, we use error codes -ECANCELED or -ETIME. This patch adds
> an error code parameter to drm_sched_start, allowing us to differentiate between queue reset and
> GPU reset failures. This enables user mode and test applications to validate the expected
> correctness of the requested operation. After a successful queue reset, the only way to continue
> normal operation is to call drm_sched_job_done with the specific error code -ENODATA.
>
> v1: Initial implementation by Jesse utilized amdgpu_device_lock_reset_domain and
> amdgpu_device_unlock_reset_domain to allow user mode to track the queue reset status and distinguish
> between queue reset and GPU reset.
> v2: Christian suggested using the error codes -ENODATA for queue reset and -ECANCELED or -ETIME for GPU
> reset, returned to amdgpu_cs_wait_ioctl.
> v3: To meet the requirements, we introduce a new function drm_sched_start_ex with an additional parameter
> to set dma_fence_set_error, allowing us to handle the specific error codes appropriately and dispose
> of bad jobs with the selected error code depending on whether it was a queue reset or GPU reset.
> v4: Alex suggested using a new name, drm_sched_start_with_recovery_error, which more accurately describes
> the function's purpose. Additionally, it was recommended to add documentation details about the new method.
>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Cc: Christian Koenig <christian.koenig at amd.com>
> Signed-off-by: Jesse Zhang <Jesse.Zhang at amd.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak at amd.com>
> ---
> drivers/gpu/drm/scheduler/sched_main.c | 30 +++++++++++++++++++++++---
> include/drm/gpu_scheduler.h | 1 +
> 2 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
> index 7e90c9f95611..c42449358b3f 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -671,13 +671,24 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
> EXPORT_SYMBOL(drm_sched_stop);
>
> /**
> - * drm_sched_start - recover jobs after a reset
> + * drm_sched_start_with_recovery_error - recover jobs after a reset with
> + * custom error
> *
> * @sched: scheduler instance
> * @full_recovery: proceed with complete sched restart
> + * @error : err code for set dma_fence_set_error
> + *
> + * Starts the scheduler and allows setting a custom dma_fence_set_error,
> + * which can be used to identify the recovery mechanism actually used.
> *
> + * For example:
> + * - If a soft or queue reset was used, dma_fence_set_error is set to -ENODATA.
> + * - If an entire GPU reset was used, the error code is set to -ECANCELED.
> + *
> + * This approach enables user mode and test applications to know which
> + * recovery method was used for a given bad job.
> */
> -void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery)
> +void drm_sched_start_with_recovery_error(struct drm_gpu_scheduler *sched, bool full_recovery, int error)
> {
> struct drm_sched_job *s_job, *tmp;
> int r;
> @@ -704,7 +715,7 @@ void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery)
> DRM_DEV_ERROR(sched->dev, "fence add callback failed (%d)\n",
> r);
> } else
> - drm_sched_job_done(s_job, -ECANCELED);
> + drm_sched_job_done(s_job, error);
> }
>
> if (full_recovery)
> @@ -712,6 +723,19 @@ void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery)
>
> drm_sched_wqueue_start(sched);
> }
> +EXPORT_SYMBOL(drm_sched_start_with_recovery_error);
> +
> +/**
> + * drm_sched_start - recover jobs after a reset
> + *
> + * @sched: scheduler instance
> + * @full_recovery: proceed with complete sched restart
> + *
> + */
> +void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery)
> +{
> + drm_sched_start_with_recovery_error(sched, full_recovery, -ECANCELED);
> +}
> EXPORT_SYMBOL(drm_sched_start);
>
> /**
> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
> index 5acc64954a88..444fa6761590 100644
> --- a/include/drm/gpu_scheduler.h
> +++ b/include/drm/gpu_scheduler.h
> @@ -580,6 +580,7 @@ void drm_sched_wqueue_stop(struct drm_gpu_scheduler *sched);
> void drm_sched_wqueue_start(struct drm_gpu_scheduler *sched);
> void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad);
> void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery);
> +void drm_sched_start_ex(struct drm_gpu_scheduler *sched, bool full_recovery, int error);
drm_sched_start_with_recovery_error()
Alex
> void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched);
> void drm_sched_increase_karma(struct drm_sched_job *bad);
> void drm_sched_reset_karma(struct drm_sched_job *bad);
> --
> 2.25.1
>
------------------------------
Message: 4
Date: Thu, 25 Jul 2024 10:35:07 -0600
From: Alex Hung <alex.hung at amd.com>
To: Melissa Wen <mwen at igalia.com>, harry.wentland at amd.com,
sunpeng.li at amd.com, Rodrigo.Siqueira at amd.com,
alexander.deucher at amd.com, christian.koenig at amd.com,
Xinhui.Pan at amd.com, airlied at gmail.com, daniel at ffwll.ch
Cc: Mario Limonciello <mario.limonciello at amd.com>, Jani Nikula
<jani.nikula at linux.intel.com>, amd-gfx at lists.freedesktop.org,
dri-devel at lists.freedesktop.org, kernel-dev at igalia.com
Subject: Re: [PATCH v4 02/11] drm/amd/display: switch
amdgpu_dm_connector to use struct drm_edid
Message-ID: <d1cce2ee-f12b-4d37-8729-5ff22cb64550 at amd.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Please see inline comments.
On 2024-07-05 21:35, Melissa Wen wrote:
> Replace raw edid handling (struct edid) with the opaque EDID type
> (struct drm_edid) on amdgpu_dm_connector for consistency. It may also
> prevent mismatch of approaches in different parts of the driver code.
> Working in progress. It was only exercised with IGT tests.
>
> v2: use const to fix warnings (Alex Hung)
> v3: fix general protection fault on mst
> v4: rename edid to drm_edid in amdgpu_connector (Jani)
> call drm_edid_connector_update to clear edid in case of NULL (Jani)
> keep setting NULL instead of free drm_edid (Jani)
> check drm_edid not NULL, instead of valid (Jani)
>
> Signed-off-by: Melissa Wen <mwen at igalia.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 106 +++++++++---------
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 +-
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 ++-
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 32 +++---
> 4 files changed, 79 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 1dfa7ec9af35..49b8c5b00728 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3408,7 +3408,7 @@ void amdgpu_dm_update_connector_after_detect(
> aconnector->dc_sink = sink;
> dc_sink_retain(aconnector->dc_sink);
> amdgpu_dm_update_freesync_caps(connector,
> - aconnector->edid);
> + aconnector->drm_edid);
> } else {
> amdgpu_dm_update_freesync_caps(connector, NULL);
> if (!aconnector->dc_sink) {
> @@ -3467,18 +3467,20 @@ void amdgpu_dm_update_connector_after_detect(
> aconnector->dc_sink = sink;
> dc_sink_retain(aconnector->dc_sink);
> if (sink->dc_edid.length == 0) {
> - aconnector->edid = NULL;
> + aconnector->drm_edid = NULL;
> if (aconnector->dc_link->aux_mode) {
> drm_dp_cec_unset_edid(
> &aconnector->dm_dp_aux.aux);
> }
> } else {
> - aconnector->edid =
> - (struct edid *)sink->dc_edid.raw_edid;
> + const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid;
> + aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length);
> + drm_edid_connector_update(connector, aconnector->drm_edid);
>
> + /* FIXME: Get rid of drm_edid_raw() */
> if (aconnector->dc_link->aux_mode)
> drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
> - aconnector->edid);
Why not pass edid but drm_edid_raw(aconnector->drm_edid)?
> + drm_edid_raw(aconnector->drm_edid));
> }
>
> if (!aconnector->timing_requested) {
> @@ -3489,17 +3491,18 @@ void amdgpu_dm_update_connector_after_detect(
> "failed to create aconnector->requested_timing\n");
> }
>
> - drm_connector_update_edid_property(connector, aconnector->edid);
> - amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
> + drm_edid_connector_update(connector, aconnector->drm_edid);
> + amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid);
> update_connector_ext_caps(aconnector);
> } else {
> drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
> amdgpu_dm_update_freesync_caps(connector, NULL);
> - drm_connector_update_edid_property(connector, NULL);
> + drm_edid_connector_update(connector, NULL);
> aconnector->num_modes = 0;
> dc_sink_release(aconnector->dc_sink);
> aconnector->dc_sink = NULL;
> - aconnector->edid = NULL;
> + drm_edid_free(aconnector->drm_edid);
> + aconnector->drm_edid = NULL;
> kfree(aconnector->timing_requested);
> aconnector->timing_requested = NULL;
> /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
> @@ -7002,13 +7005,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
> struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
> struct dc_link *dc_link = aconnector->dc_link;
> struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
> - struct edid *edid;
> - struct i2c_adapter *ddc;
> -
> - if (dc_link && dc_link->aux_mode)
> - ddc = &aconnector->dm_dp_aux.aux.ddc;
> - else
> - ddc = &aconnector->i2c->base;
> + const struct drm_edid *drm_edid;
>
> /*
> * Note: drm_get_edid gets edid in the following order:
> @@ -7016,18 +7013,20 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
> * 2) firmware EDID if set via edid_firmware module parameter
> * 3) regular DDC read.
> */
> - edid = drm_get_edid(connector, ddc);
drm_get_edid() is removed here, and thhe above comments should be
removed as well.
> - if (!edid) {
> + drm_edid = drm_edid_read(connector);
> + drm_edid_connector_update(connector, drm_edid);
> + if (!drm_edid) {
> DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
> return;
> }
>
> - aconnector->edid = edid;
> -
> + aconnector->drm_edid = drm_edid;
> /* Update emulated (virtual) sink's EDID */
> if (dc_em_sink && dc_link) {
> + const struct edid *edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
> +
> memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
> - memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
> + memmove(dc_em_sink->dc_edid.raw_edid, (uint8_t *)edid, (edid->extensions + 1) * EDID_LENGTH);
is casting to (uint8 *) necessary?
> dm_helpers_parse_edid_caps(
> dc_link,
> &dc_em_sink->dc_edid,
> @@ -7057,18 +7056,12 @@ static int get_modes(struct drm_connector *connector)
> static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
> {
> struct drm_connector *connector = &aconnector->base;
> - struct dc_link *dc_link = aconnector->dc_link;
> struct dc_sink_init_data init_params = {
> .link = aconnector->dc_link,
> .sink_signal = SIGNAL_TYPE_VIRTUAL
> };
> - struct edid *edid;
> - struct i2c_adapter *ddc;
> -
> - if (dc_link->aux_mode)
> - ddc = &aconnector->dm_dp_aux.aux.ddc;
> - else
> - ddc = &aconnector->i2c->base;
> + const struct drm_edid *drm_edid;
> + const struct edid *edid;
>
> /*
> * Note: drm_get_edid gets edid in the following order:
> @@ -7076,17 +7069,19 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
> * 2) firmware EDID if set via edid_firmware module parameter
> * 3) regular DDC read.
> */
> - edid = drm_get_edid(connector, ddc);
drm_get_edid() is removed here, and thhe above comments should be
removed as well.
> - if (!edid) {
> + drm_edid = drm_edid_read(connector);
> + drm_edid_connector_update(connector, drm_edid);
> + if (!drm_edid) {
> DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
> return;
> }
>
> - if (drm_detect_hdmi_monitor(edid))
> + if (connector->display_info.is_hdmi)
> init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
>
> - aconnector->edid = edid;
> + aconnector->drm_edid = drm_edid;
>
> + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
> aconnector->dc_em_sink = dc_link_add_remote_sink(
> aconnector->dc_link,
> (uint8_t *)edid,
> @@ -7770,16 +7765,16 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector)
> }
>
> static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
> - struct edid *edid)
> + const struct drm_edid *drm_edid)
> {
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
>
> - if (edid) {
> + if (drm_edid) {
> /* empty probed_modes */
> INIT_LIST_HEAD(&connector->probed_modes);
> amdgpu_dm_connector->num_modes =
> - drm_add_edid_modes(connector, edid);
> + drm_edid_connector_add_modes(connector);
>
> /* sorting the probed modes before calling function
> * amdgpu_dm_get_native_mode() since EDID can have
> @@ -7793,10 +7788,10 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
> amdgpu_dm_get_native_mode(connector);
>
> /* Freesync capabilities are reset by calling
> - * drm_add_edid_modes() and need to be
> + * drm_edid_connector_add_modes() and need to be
> * restored here.
> */
> - amdgpu_dm_update_freesync_caps(connector, edid);
> + amdgpu_dm_update_freesync_caps(connector, drm_edid);
> } else {
> amdgpu_dm_connector->num_modes = 0;
> }
> @@ -7892,12 +7887,12 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
> }
>
> static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
> - struct edid *edid)
> + const struct drm_edid *drm_edid)
> {
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
>
> - if (!(amdgpu_freesync_vid_mode && edid))
> + if (!(amdgpu_freesync_vid_mode && drm_edid))
> return;
>
> if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
> @@ -7910,24 +7905,24 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
> struct drm_encoder *encoder;
> - struct edid *edid = amdgpu_dm_connector->edid;
> + const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid;
> struct dc_link_settings *verified_link_cap =
> &amdgpu_dm_connector->dc_link->verified_link_cap;
> const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
>
> encoder = amdgpu_dm_connector_to_encoder(connector);
>
> - if (!drm_edid_is_valid(edid)) {
> + if (!drm_edid) {
> amdgpu_dm_connector->num_modes =
> drm_add_modes_noedid(connector, 640, 480);
> if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
> amdgpu_dm_connector->num_modes +=
> drm_add_modes_noedid(connector, 1920, 1080);
> } else {
> - amdgpu_dm_connector_ddc_get_modes(connector, edid);
> + amdgpu_dm_connector_ddc_get_modes(connector, drm_edid);
> if (encoder)
> amdgpu_dm_connector_add_common_modes(encoder, connector);
> - amdgpu_dm_connector_add_freesync_modes(connector, edid);
> + amdgpu_dm_connector_add_freesync_modes(connector, drm_edid);
> }
> amdgpu_dm_fbc_init(connector);
>
> @@ -11867,7 +11862,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
> }
>
> static void parse_edid_displayid_vrr(struct drm_connector *connector,
> - struct edid *edid)
> + const struct edid *edid)
> {
> u8 *edid_ext = NULL;
> int i;
> @@ -11910,7 +11905,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector,
> }
>
> static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
> - struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
> + const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
> {
> u8 *edid_ext = NULL;
> int i;
> @@ -11945,7 +11940,8 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
> }
>
> static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
> - struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
> + const struct edid *edid,
> + struct amdgpu_hdmi_vsdb_info *vsdb_info)
> {
> u8 *edid_ext = NULL;
> int i;
> @@ -11987,19 +11983,19 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
> * FreeSync parameters.
> */
> void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> - struct edid *edid)
> + const struct drm_edid *drm_edid)
> {
> int i = 0;
> - struct detailed_timing *timing;
> - struct detailed_non_pixel *data;
> - struct detailed_data_monitor_range *range;
> + const struct detailed_timing *timing;
> + const struct detailed_non_pixel *data;
> + const struct detailed_data_monitor_range *range;
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
> struct dm_connector_state *dm_con_state = NULL;
> struct dc_sink *sink;
> -
> struct amdgpu_device *adev = drm_to_adev(connector->dev);
> struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
> + const struct edid *edid;
> bool freesync_capable = false;
> enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
>
> @@ -12012,7 +12008,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> amdgpu_dm_connector->dc_sink :
> amdgpu_dm_connector->dc_em_sink;
>
> - if (!edid || !sink) {
> + if (!drm_edid || !sink) {
> dm_con_state = to_dm_connector_state(connector->state);
>
> amdgpu_dm_connector->min_vfreq = 0;
> @@ -12029,6 +12025,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> if (!adev->dm.freesync_module)
> goto update;
>
> + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
> +
> /* Some eDP panels only have the refresh rate range info in DisplayID */
> if ((connector->display_info.monitor_range.min_vfreq == 0 ||
> connector->display_info.monitor_range.max_vfreq == 0))
> @@ -12105,7 +12103,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
> }
>
> - } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> + } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
> if (i >= 0 && vsdb_info.freesync_supported) {
> amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index 5fd1b6b44577..2aff4c4b76de 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -658,7 +658,7 @@ struct amdgpu_dm_connector {
>
> /* we need to mind the EDID between detect
> and get modes due to analog/digital/tvencoder */
> - struct edid *edid;
> + const struct drm_edid *drm_edid;
>
> /* shared with amdgpu */
> struct amdgpu_hpd hpd;
> @@ -936,7 +936,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev,
> struct drm_connector *connector);
>
> void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> - struct edid *edid);
> + const struct drm_edid *drm_edid);
>
> void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index b490ae67b6be..be72f14f5429 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -897,7 +897,8 @@ enum dc_edid_status dm_helpers_read_local_edid(
> struct i2c_adapter *ddc;
> int retry = 3;
> enum dc_edid_status edid_status;
> - struct edid *edid;
> + const struct drm_edid *drm_edid;
> + const struct edid *edid;
>
> if (link->aux_mode)
> ddc = &aconnector->dm_dp_aux.aux.ddc;
> @@ -909,25 +910,27 @@ enum dc_edid_status dm_helpers_read_local_edid(
> */
> do {
>
> - edid = drm_get_edid(&aconnector->base, ddc);
> + drm_edid = drm_edid_read_ddc(connector, ddc);
> + drm_edid_connector_update(connector, drm_edid);
>
> /* DP Compliance Test 4.2.2.6 */
> if (link->aux_mode && connector->edid_corrupt)
> drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
>
> - if (!edid && connector->edid_corrupt) {
> + if (!drm_edid && connector->edid_corrupt) {
> connector->edid_corrupt = false;
> return EDID_BAD_CHECKSUM;
> }
>
> - if (!edid)
> + if (!drm_edid)
> return EDID_NO_RESPONSE;
>
> + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
> sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
> memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
>
> /* We don't need the original edid anymore */
> - kfree(edid);
> + drm_edid_free(drm_edid);
>
> edid_status = dm_helpers_parse_edid_caps(
> link,
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 5442da90f508..b0d307e5dd72 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -129,7 +129,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)
> dc_sink_release(aconnector->dc_sink);
> }
>
> - kfree(aconnector->edid);
> + drm_edid_free(aconnector->drm_edid);
>
> drm_connector_cleanup(connector);
> drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
> @@ -182,7 +182,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
>
> dc_sink_release(dc_sink);
> aconnector->dc_sink = NULL;
> - aconnector->edid = NULL;
> + aconnector->drm_edid = NULL;
> aconnector->dsc_aux = NULL;
> port->passthrough_aux = NULL;
> }
> @@ -302,16 +302,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
> if (!aconnector)
> return drm_add_edid_modes(connector, NULL);
>
> - if (!aconnector->edid) {
> - struct edid *edid;
> + if (!aconnector->drm_edid) {
> + const struct drm_edid *drm_edid;
>
> - edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port);
> + drm_edid = drm_dp_mst_edid_read(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port);
>
> - if (!edid) {
> + if (!drm_edid) {
> amdgpu_dm_set_mst_status(&aconnector->mst_status,
> MST_REMOTE_EDID, false);
>
> - drm_connector_update_edid_property(
> + drm_edid_connector_update(
> &aconnector->base,
> NULL);
>
> @@ -345,7 +345,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
> return ret;
> }
>
> - aconnector->edid = edid;
> + aconnector->drm_edid = drm_edid;
> amdgpu_dm_set_mst_status(&aconnector->mst_status,
> MST_REMOTE_EDID, true);
> }
> @@ -360,10 +360,13 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
> struct dc_sink_init_data init_params = {
> .link = aconnector->dc_link,
> .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
> + const struct edid *edid;
> +
> + edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw()
> dc_sink = dc_link_add_remote_sink(
> aconnector->dc_link,
> - (uint8_t *)aconnector->edid,
> - (aconnector->edid->extensions + 1) * EDID_LENGTH,
> + (uint8_t *)edid,
> + (edid->extensions + 1) * EDID_LENGTH,
> &init_params);
>
> if (!dc_sink) {
> @@ -405,7 +408,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
>
> if (aconnector->dc_sink) {
> amdgpu_dm_update_freesync_caps(
> - connector, aconnector->edid);
> + connector, aconnector->drm_edid);
>
> #if defined(CONFIG_DRM_AMD_DC_FP)
> if (!validate_dsc_caps_on_connector(aconnector))
> @@ -419,10 +422,9 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
> }
> }
>
> - drm_connector_update_edid_property(
> - &aconnector->base, aconnector->edid);
> + drm_edid_connector_update(&aconnector->base, aconnector->drm_edid);
>
> - ret = drm_add_edid_modes(connector, aconnector->edid);
> + ret = drm_edid_connector_add_modes(connector);
>
> return ret;
> }
> @@ -500,7 +502,7 @@ dm_dp_mst_detect(struct drm_connector *connector,
>
> dc_sink_release(aconnector->dc_sink);
> aconnector->dc_sink = NULL;
> - aconnector->edid = NULL;
> + aconnector->drm_edid = NULL;
> aconnector->dsc_aux = NULL;
> port->passthrough_aux = NULL;
>
------------------------------
Subject: Digest Footer
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------------------------------
End of amd-gfx Digest, Vol 98, Issue 341
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