[PATCH v2 2/5] drm/amd/display: Go through dm for allow_idle_optimizations

sunpeng.li at amd.com sunpeng.li at amd.com
Mon Aug 19 19:22:14 UTC 2024


From: Leo Li <sunpeng.li at amd.com>

[Why]

In preparation for enabling IPS debug flags that require DM changes,
a common entry point for allowing DC idle optimisations is needed.

[How]

Create an alias in DM for dc_allow_idle_optimizations(). Change all
calls to it into dm_allow_idle_optimizations().

No functional changes are intended.

Signed-off-by: Leo Li <sunpeng.li at amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    | 16 ++++++++++++----
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h    |  6 ++++++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c   |  8 ++++----
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c    |  2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c    |  2 +-
 5 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a18ecf8607232..2efa9f6e23015 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -246,6 +246,14 @@ static void handle_hpd_rx_irq(void *param);
 static bool
 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 				 struct drm_crtc_state *new_crtc_state);
+
+void dm_allow_idle_optimizations_internal(struct dc *dc,
+					  bool allow,
+					  char const *caller_name)
+{
+	dc_allow_idle_optimizations_internal(dc, allow, caller_name);
+}
+
 /*
  * dm_vblank_get_counter
  *
@@ -296,7 +304,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 	}
 
 	if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
-		dc_allow_idle_optimizations(dc, false);
+		dm_allow_idle_optimizations(dc, false);
 
 	/*
 	 * TODO rework base driver to use values directly.
@@ -2883,7 +2891,7 @@ static int dm_suspend(void *handle)
 	if (amdgpu_in_reset(adev)) {
 		mutex_lock(&dm->dc_lock);
 
-		dc_allow_idle_optimizations(adev->dm.dc, false);
+		dm_allow_idle_optimizations(adev->dm.dc, false);
 
 		dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
 
@@ -2911,7 +2919,7 @@ static int dm_suspend(void *handle)
 	hpd_rx_irq_work_suspend(dm);
 
 	if (adev->dm.dc->caps.ips_support)
-		dc_allow_idle_optimizations(adev->dm.dc, true);
+		dm_allow_idle_optimizations(adev->dm.dc, true);
 
 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 	dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
@@ -9421,7 +9429,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
 
 	/* Allow idle optimization when vblank count is 0 for display off */
 	if (dm->active_vblank_irq_count == 0)
-		dc_allow_idle_optimizations(dm->dc, true);
+		dm_allow_idle_optimizations(dm->dc, true);
 	mutex_unlock(&dm->dc_lock);
 
 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2d7755e2b6c32..3fc3c12b3a4a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -1007,4 +1007,10 @@ void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
 
 bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
 
+void dm_allow_idle_optimizations_internal(struct dc *dc,
+					  bool allow,
+					  char const *caller_name);
+#define dm_allow_idle_optimizations(dc, allow) \
+	dm_allow_idle_optimizations_internal(dc, allow, __func__)
+
 #endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index a2cf2c066a76d..5b0d426ad50db 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -203,7 +203,7 @@ static void amdgpu_dm_idle_worker(struct work_struct *work)
 			mutex_unlock(&idle_work->dm->dc_lock);
 			break;
 		}
-		dc_allow_idle_optimizations(idle_work->dm->dc, false);
+		dm_allow_idle_optimizations(idle_work->dm->dc, false);
 
 		mutex_unlock(&idle_work->dm->dc_lock);
 		fsleep(HPD_DETECTION_TIME_uS);
@@ -216,7 +216,7 @@ static void amdgpu_dm_idle_worker(struct work_struct *work)
 		}
 
 		if (idle_work->enable)
-			dc_allow_idle_optimizations(idle_work->dm->dc, true);
+			dm_allow_idle_optimizations(idle_work->dm->dc, true);
 		mutex_unlock(&idle_work->dm->dc_lock);
 	}
 	idle_work->dm->idle_workqueue->running = false;
@@ -253,7 +253,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 
 	if (dm->active_vblank_irq_count > 0) {
 		DRM_DEBUG_KMS("Allow idle optimizations (MALL): false\n");
-		dc_allow_idle_optimizations(dm->dc, false);
+		dm_allow_idle_optimizations(dm->dc, false);
 	}
 
 	/*
@@ -275,7 +275,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 
 	if (dm->active_vblank_irq_count == 0) {
 		DRM_DEBUG_KMS("Allow idle optimizations (MALL): true\n");
-		dc_allow_idle_optimizations(dm->dc, true);
+		dm_allow_idle_optimizations(dm->dc, true);
 	}
 
 	mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 3390f0d8420a0..48a4c493a70a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -730,7 +730,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
 	st = (state == AMDGPU_IRQ_STATE_ENABLE);
 
 	if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
-		dc_allow_idle_optimizations(dc, false);
+		dm_allow_idle_optimizations(dc, false);
 
 	dc_interrupt_set(adev->dm.dc, irq_source, st);
 	return 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index f40240aafe988..fdf1d4c7b9300 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -192,7 +192,7 @@ void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 	dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
 
 	if (link->ctx->dc->caps.ips_support)
-		dc_allow_idle_optimizations(link->ctx->dc, true);
+		dm_allow_idle_optimizations(link->ctx->dc, true);
 }
 
 /*
-- 
2.46.0



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