[PATCH 3/3] drm/amdgpu/pm: Implement SDMA queue reset for different asic

Huang, Tim Tim.Huang at amd.com
Tue Dec 17 01:06:05 UTC 2024


[AMD Official Use Only - AMD Internal Distribution Only]

Looks ok to me.  This Series is,

Reviewed-by: Tim Huang <tim.huang at amd.com<mailto:tim.huang at amd.com>>



________________________________
From: Jesse.zhang at amd.com <jesse.zhang at amd.com>
Sent: Monday, December 16, 2024 5:29:56 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Huang, Tim <Tim.Huang at amd.com>; Zhu, Jiadong <Jiadong.Zhu at amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>; Huang, Tim <Tim.Huang at amd.com>
Subject: [PATCH 3/3] drm/amdgpu/pm: Implement SDMA queue reset for different asic

Implement sdma queue reset by SMU_MSG_ResetSDMA2

Suggested-by: Tim Huang <tim.huang at amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang at amd.com>
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 30 ++++++++++++++-----
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 9222e7a777a6..446959145058 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2721,17 +2721,31 @@ static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)

 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
 {
-       struct amdgpu_device *adev = smu->adev;
+       uint32_t smu_program;
         int ret = 0;

-       /* the message is only valid on SMU 13.0.6 with pmfw 85.121.00 and above */
-       if ((adev->flags & AMD_IS_APU) ||
-           amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6) ||
-           smu->smc_fw_version < 0x00557900)
-               return 0;
+       smu_program = (smu->smc_fw_version >> 24) & 0xff;
+       switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
+       case IP_VERSION(13, 0, 6):
+               if (((smu_program == 7) && (smu->smc_fw_version > 0x07550763)) ||
+                       ((smu_program == 0) && (smu->smc_fw_version > 0x00557700)))
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                               SMU_MSG_ResetSDMA, inst_mask, NULL);
+               else if ((smu_program == 4) &&
+                       (smu->smc_fw_version > 0x4556e6c))
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                     SMU_MSG_ResetSDMA2, inst_mask, NULL);
+               break;
+       case IP_VERSION(13, 0, 14):
+               if ((smu_program == 5) &&
+                       (smu->smc_fw_version > 0x05550f00))
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                     SMU_MSG_ResetSDMA2, inst_mask, NULL);
+               break;
+       default:
+               break;
+       }

-       ret = smu_cmn_send_smc_msg_with_param(smu,
-                                             SMU_MSG_ResetSDMA, inst_mask, NULL);
         if (ret)
                 dev_err(smu->adev->dev,
                         "failed to send ResetSDMA event with mask 0x%x\n",
--
2.25.1


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