[PATCH 04/17] drm/amd/display: Add SMU timeout check and retry

Hamza Mahfooz hamza.mahfooz at amd.com
Wed Feb 14 18:47:01 UTC 2024


On 2/14/24 13:38, Rodrigo Siqueira wrote:
> Instead of only asserting in the case of the SMU wait time is not what
> we expect, add the SMU timeout check and try again.
> 
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>

Acked-by: Hamza Mahfooz <hamza.mahfooz at amd.com>

> ---
>   .../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 11 ++++++++---
>   .../drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c    |  6 +++++-
>   2 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> index d72acbb049b1..23b390245b5d 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
> @@ -26,6 +26,10 @@
>   #include "core_types.h"
>   #include "clk_mgr_internal.h"
>   #include "reg_helper.h"
> +#include "dm_helpers.h"
> +
> +#include "rn_clk_mgr_vbios_smu.h"
> +
>   #include <linux/delay.h>
>   
>   #include "renoir_ip_offset.h"
> @@ -33,8 +37,6 @@
>   #include "mp/mp_12_0_0_offset.h"
>   #include "mp/mp_12_0_0_sh_mask.h"
>   
> -#include "rn_clk_mgr_vbios_smu.h"
> -
>   #define REG(reg_name) \
>   	(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
>   
> @@ -120,7 +122,10 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
>   
>   	result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
>   
> -	ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
> +	if (IS_SMU_TIMEOUT(result)) {
> +		ASSERT(0);
> +		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
> +	}
>   
>   	/* Actual dispclk set is returned in the parameter register */
>   	return REG_READ(MP1_SMN_C2PMSG_83);
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
> index 19e5b3be9275..b4fb17b7a096 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
> @@ -29,6 +29,7 @@
>   #include <linux/delay.h>
>   
>   #include "dcn301_smu.h"
> +#include "dm_helpers.h"
>   
>   #include "vangogh_ip_offset.h"
>   
> @@ -120,7 +121,10 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
>   
>   	result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
>   
> -	ASSERT(result == VBIOSSMC_Result_OK);
> +	if (IS_SMU_TIMEOUT(result)) {
> +		ASSERT(0);
> +		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
> +	}
>   
>   	/* Actual dispclk set is returned in the parameter register */
>   	return REG_READ(MP1_SMN_C2PMSG_83);
-- 
Hamza



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