[PATCH] drm/amdgpu: reserve more memory for MES runtime DRAM

[Zhang, Yifan]

[AMD Official Use Only - General]

This patch is :

Reviewed-by: Yifan Zhang <yifan1.zhang at amd.com>

Best Regards,
Yifan

-----Original Message-----
From: Huang, Tim <Tim.Huang at amd.com>
Sent: Friday, February 23, 2024 2:38 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Yifan <Yifan1.Zhang at amd.com>; Huang, Tim <Tim.Huang at amd.com>
Subject: [PATCH] drm/amdgpu: reserve more memory for MES runtime DRAM

This patch fixes a MES firmware boot failure issue when backdoor loading the MES firmware.

MES firmware runtime DRAM size is changed to 512k, the driver needs to reserve this amount of memory in FB, otherwise adjacent memory will be overwritten by the MES firmware startup code.

Signed-off-by: Tim Huang <Tim.Huang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 26d71a22395d..36127e204dfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -56,6 +56,7 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);  static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);

 #define MES_EOP_SIZE   2048
+#define GFX_MES_DRAM_SIZE      0x80000

 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)  { @@ -475,7 +476,13 @@ static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
                   le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
        fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);

-       r = amdgpu_bo_create_reserved(adev, fw_size,
+       if (fw_size > GFX_MES_DRAM_SIZE) {
+               dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
+                       pipe, fw_size, GFX_MES_DRAM_SIZE);
+               return -EINVAL;
+       }
+
+       r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
                                      64 * 1024,
                                      AMDGPU_GEM_DOMAIN_VRAM |
                                      AMDGPU_GEM_DOMAIN_GTT,
@@ -611,8 +618,8 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
        WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
                     upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));

-       /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
-       WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
+       /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
+       WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);

        if (prime_icache) {
                /* invalidate ICACHE */
--
2.39.2