[PATCH v2 v2 2/5] drm/amdgpu: Init pcie_index/data address as fallback (v2)

[Wang, Yang(Kevin)]

[AMD Official Use Only - General]

-----Original Message-----
From: Hawking Zhang <Hawking.Zhang at amd.com>
Sent: Sunday, January 7, 2024 11:40 PM
To: amd-gfx at lists.freedesktop.org; Zhou1, Tao <Tao.Zhou1 at amd.com>; Yang, Stanley <Stanley.Yang at amd.com>; Wang, Yang(Kevin) <KevinYang.Wang at amd.com>; Chai, Thomas <YiPeng.Chai at amd.com>; Li, Candice <Candice.Li at amd.com>
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Lazar, Lijo <Lijo.Lazar at amd.com>; Ma, Le <Le.Ma at amd.com>
Subject: [PATCH v2 v2 2/5] drm/amdgpu: Init pcie_index/data address as fallback (v2)

To allow using this helper for indirect access when nbio funcs is not available. For instance, in ip discovery phase.

v2: define macro for pcie_index/data/index_hi fallback.

Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abad5773714c..05d7cdcf28b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -96,6 +96,9 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
 #define AMDGPU_RESUME_MS               2000
 #define AMDGPU_MAX_RETRY_LIMIT         2
 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
+#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) #define
+AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) #define
+AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2)

 static const struct drm_driver amdgpu_kms_driver;

@@ -781,12 +784,22 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
        void __iomem *pcie_index_hi_offset;
        void __iomem *pcie_data_offset;

-       pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
-       pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
-       if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
-               pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
-       else
+       if (unlikely(!adev->nbio.funcs)) {
+               pcie_index = AMDGPU_PCIE_INDEX_FALLBACK;
+               pcie_data = AMDGPU_PCIE_DATA_FALLBACK;
+       } else {
+               pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
+               pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
+       }
+
+       if (reg_addr >> 32) {
[kevin]:
Gentle reminder that the macro 'upper_32_bits()' can help on it .

Series is.
Reviewed-by: Yang Wang <kevinyang.wang at amd.com>

Best Regards,
Kevin
+               if (unlikely(!adev->nbio.funcs))
+                       pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK;
+               else
+                       pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
+       } else {
                pcie_index_hi = 0;
+       }

        spin_lock_irqsave(&adev->pcie_idx_lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
--
2.17.1