[PATCH 4/4] drm/amdgpu: Do not program VM_L2_CNTL under SRIOV

[Chander, Vignesh]

[AMD Official Use Only - General]

Reviewed-by: Vignesh Chander <Vignesh.Chander at amd.com>

-----Original Message-----
From: Victor Lu <victorchengchi.lu at amd.com>
Sent: Tuesday, January 2, 2024 12:30 PM
To: amd-gfx at lists.freedesktop.org
Cc: Chander, Vignesh <Vignesh.Chander at amd.com>; Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu at amd.com>
Subject: [PATCH 4/4] drm/amdgpu: Do not program VM_L2_CNTL under SRIOV

VM_L2_CNTL* should not be programmed on driver unload under SRIOV.
These regs are skipped during SRIOV driver init.

Signed-off-by: Victor Lu <victorchengchi.lu at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 55423ff1bb49..20e800bc0b68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -454,10 +454,12 @@ static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev,
                WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);

                /* Setup L2 cache */
-               tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
-               tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
-               WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
-               WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
+               if (!amdgpu_sriov_vf(adev)) {
+                       tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
+                       tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
+                       WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
+                       WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
+               }
        }
 }

--
2.34.1