[PATCH 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3

[Zhang, Yifan]

[AMD Official Use Only - General]

Hi Tim,

Thanks for pointing this out. Will change it in V2.

Best Regards,
Yifan

-----Original Message-----
From: Huang, Tim <Tim.Huang at amd.com>
Sent: Tuesday, January 9, 2024 10:58 AM
To: Zhang, Yifan <Yifan1.Zhang at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Yifan <Yifan1.Zhang at amd.com>; Yu, Lang <Lang.Yu at amd.com>; Ma, Li <Li.Ma at amd.com>
Subject: RE: [PATCH 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3

[AMD Official Use Only - General]

Hi Yifan,

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Yifan Zhang
Sent: Tuesday, January 9, 2024 10:06 AM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Yifan <Yifan1.Zhang at amd.com>; Yu, Lang <Lang.Yu at amd.com>; Ma, Li <Li.Ma at amd.com>
Subject: [PATCH 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3

This patch to update ATHUB_MISC_CNTL offset for nbio v3.3

Signed-off-by: Yifan Zhang <yifan1.zhang at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
index f0737fb3a999..644dbae9f1d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
@@ -30,6 +30,8 @@

 #define regATHUB_MISC_CNTL_V3_0_1                      0x00d7
 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX             0
+#define regATHUB_MISC_CNTL_V3_3_0                      0x00d8
+#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX             0


 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) @@ -40,6 +42,9 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
        case IP_VERSION(3, 0, 1):
                data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);
                break;
+       case IP_VERSION(3, 3, 0):
+               data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);
+               break;
        default:
                data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
                break;
@@ -53,6 +58,9 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
        case IP_VERSION(3, 0, 1):
                WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);
                break;
+       case IP_VERSION(3, 3, 0):
+               data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);

                            Is this a typo? It should be WREG32_SOC15. Thanks.

                Best Regards,
                Tim Huang

+               break;
        default:
                WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
                break;
--
2.37.3