[PATCH v2] drm/amdgpu: drm/amdgpu: remove golden setting for gfx 11.5.0

[Yu, Lang]

[Public]

Reviewed-by: Lang Yu <lang.yu at amd.com>

>-----Original Message-----
>From: Zhang, Yifan <Yifan1.Zhang at amd.com>
>Sent: Tuesday, January 30, 2024 1:20 PM
>To: amd-gfx at lists.freedesktop.org
>Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian
><Christian.Koenig at amd.com>; Huang, Tim <Tim.Huang at amd.com>; Yu, Lang
><Lang.Yu at amd.com>; Zhang, Yifan <Yifan1.Zhang at amd.com>
>Subject: [PATCH v2] drm/amdgpu: drm/amdgpu: remove golden setting for gfx
>11.5.0
>
>No need to set GC golden settings in driver from gfx 11.5.0 onwards.
>
>Signed-off-by: Yifan Zhang <yifan1.zhang at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 22 ----------------------
> 1 file changed, 22 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>index c1e000010760..2fb1342d5bd9 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>@@ -107,23 +107,6 @@ static const struct soc15_reg_golden
>golden_settings_gc_11_0_1[] =
>       SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff,
>0x0000000a)  };
>
>-static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff,
>0x00000800),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff,
>0x00000242),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff,
>0x00000500),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK,
>0xffffffff, 0xfffffff3),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK,
>0xffffffff, 0xfffffff3),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb,
>0x00f40188),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff,
>0x80009007),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff,
>0x00880007),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff,
>0x00010000),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff,
>0x01030000),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000,
>0x00000000),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff,
>0x0000200a),
>-      SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff,
>0x0000048f)
>-};
>-
> #define DEFAULT_SH_MEM_CONFIG \
>       ((SH_MEM_ADDRESS_MODE_64 <<
>SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
>        (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
>SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ @@ -304,11 +287,6 @@
>static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
>                                               golden_settings_gc_11_0_1,
>                                               (const
>u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
>               break;
>-      case IP_VERSION(11, 5, 0):
>-              soc15_program_register_sequence(adev,
>-                                              golden_settings_gc_11_5_0,
>-                                              (const
>u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
>-              break;
>       default:
>               break;
>       }
>--
>2.37.3