[PATCH v1 4/4] drm/amdgpu: add gfx queue support for gfx12 ipdump
Alex Deucher
alexdeucher at gmail.com
Wed Jul 3 14:28:57 UTC 2024
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
On Wed, Jul 3, 2024 at 3:39 AM Sunil Khatri <sunil.khatri at amd.com> wrote:
>
> Add support of all the CP GFX queues for gfx12 ipdump
> to be used by devcoredump.
>
> Signed-off-by: Sunil Khatri <sunil.khatri at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 94 ++++++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 21b8167f39bd..cf7209b93617 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -173,6 +173,35 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
> SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
> };
>
> +static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
> + /* gfx queue registers */
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
> +};
> +
> #define DEFAULT_SH_MEM_CONFIG \
> ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
> (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
> @@ -1265,6 +1294,19 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
> } else {
> adev->gfx.ip_dump_compute_queues = ptr;
> }
> +
> + /* Allocate memory for gfx queue registers for all the instances */
> + reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
> + inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
> + adev->gfx.me.num_queue_per_pipe;
> +
> + ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
> + if (ptr == NULL) {
> + DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
> + adev->gfx.ip_dump_gfx_queues = NULL;
> + } else {
> + adev->gfx.ip_dump_gfx_queues = ptr;
> + }
> }
>
> static int gfx_v12_0_sw_init(void *handle)
> @@ -1462,6 +1504,7 @@ static int gfx_v12_0_sw_fini(void *handle)
>
> kfree(adev->gfx.ip_dump_core);
> kfree(adev->gfx.ip_dump_compute_queues);
> + kfree(adev->gfx.ip_dump_gfx_queues);
>
> return 0;
> }
> @@ -4853,6 +4896,31 @@ static void gfx_v12_ip_print(void *handle, struct drm_printer *p)
> }
> }
> }
> +
> + /* print gfx queue registers for all instances */
> + if (!adev->gfx.ip_dump_gfx_queues)
> + return;
> +
> + index = 0;
> + reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
> + drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
> + adev->gfx.me.num_me,
> + adev->gfx.me.num_pipe_per_me,
> + adev->gfx.me.num_queue_per_pipe);
> +
> + for (i = 0; i < adev->gfx.me.num_me; i++) {
> + for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
> + for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
> + drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
> + for (reg = 0; reg < reg_count; reg++) {
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + gc_gfx_queue_reg_list_12[reg].reg_name,
> + adev->gfx.ip_dump_gfx_queues[index + reg]);
> + }
> + index += reg_count;
> + }
> + }
> + }
> }
>
> static void gfx_v12_ip_dump(void *handle)
> @@ -4893,6 +4961,32 @@ static void gfx_v12_ip_dump(void *handle)
> soc24_grbm_select(adev, 0, 0, 0, 0);
> mutex_unlock(&adev->srbm_mutex);
> amdgpu_gfx_off_ctrl(adev, true);
> +
> + /* dump gfx queue registers for all instances */
> + if (!adev->gfx.ip_dump_gfx_queues)
> + return;
> +
> + index = 0;
> + reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
> + amdgpu_gfx_off_ctrl(adev, false);
> + mutex_lock(&adev->srbm_mutex);
> + for (i = 0; i < adev->gfx.me.num_me; i++) {
> + for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
> + for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
> + soc24_grbm_select(adev, i, j, k, 0);
> +
> + for (reg = 0; reg < reg_count; reg++) {
> + adev->gfx.ip_dump_gfx_queues[index + reg] =
> + RREG32(SOC15_REG_ENTRY_OFFSET(
> + gc_gfx_queue_reg_list_12[reg]));
> + }
> + index += reg_count;
> + }
> + }
> + }
> + soc24_grbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> + amdgpu_gfx_off_ctrl(adev, true);
> }
>
> static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
> --
> 2.34.1
>
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