[PATCH v1 2/2] drm/amdgpu: enable redirection of irq's for IH v7.0

[Alex Deucher]

Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

On Wed, Jul 3, 2024 at 1:49 PM Sunil Khatri <sunil.khatri at amd.com> wrote:
>
> Enable redirection of irq for pagefaults for specific
> clients to avoid overflow without dropping interrupts.
>
> So here we redirect the interrupts to another IH ring
> i.e ring1 where only these interrupts are processed.
>
> Signed-off-by: Sunil Khatri <sunil.khatri at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index 548b3c63a765..6852081fcff2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -346,6 +346,21 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev)
>                             DELAY, 3);
>         WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
>
> +       /* Redirect the interrupts to IH RB1 for dGPU */
> +       if (adev->irq.ih1.ring_size) {
> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
> +
> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
> +                                   SOURCE_ID_MATCH_ENABLE, 0x1);
> +
> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
> +       }
> +
>         pci_set_master(adev->pdev);
>
>         /* enable interrupts */
> --
> 2.34.1
>