[PATCH] drm/amd/swsmu: enable Pstates profile levels for SMU v14.0.4

[Alex Deucher]

On Wed, Jul 10, 2024 at 5:50 AM Li Ma <li.ma at amd.com> wrote:
>
> Enables following UMD stable Pstates profile levels
> of power_dpm_force_performance_level for SMU v14.0.4.
>
>     - profile_peak
>     - profile_min_mclk
>     - profile_min_sclk
>     - profile_standard
>
> Signed-off-by: Li Ma <li.ma at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c   | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 5d47d58944f6..8798ebfcea83 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -69,6 +69,9 @@
>  #define SMU_14_0_0_UMD_PSTATE_SOCCLK                   678
>  #define SMU_14_0_0_UMD_PSTATE_FCLK                     1800
>
> +#define SMU_14_0_4_UMD_PSTATE_GFXCLK                   938
> +#define SMU_14_0_4_UMD_PSTATE_SOCCLK                   938
> +
>  #define FEATURE_MASK(feature) (1ULL << feature)
>  #define SMC_DPM_FEATURE ( \
>         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
> @@ -1296,19 +1299,28 @@ static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
>         switch (clk_type) {
>         case SMU_GFXCLK:
>         case SMU_SCLK:
> -               clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> +               if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))
> +                       clk_limit = SMU_14_0_4_UMD_PSTATE_GFXCLK;
> +               else
> +                       clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
>                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
>                         smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
>                 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
>                         smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
>                 break;
>         case SMU_SOCCLK:
> -               clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
> +               if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))
> +                       clk_limit = SMU_14_0_4_UMD_PSTATE_SOCCLK;
> +               else
> +                       clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
>                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
>                         smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
>                 break;
>         case SMU_FCLK:
> -               clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
> +               if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4))
> +                       smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
> +               else
> +                       clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
>                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
>                         smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
>                 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
> --
> 2.25.1
>