[PATCH 2/2] drm/amdgpu/vcn: not pause dpg for unified queue

[Dong, Ruijing]

[AMD Official Use Only - AMD Internal Distribution Only]

Just change the commit messages from "For previous generations" to " For VCN3 and before" to be more specific.

With that all patches are
Reviewed-by: Ruijing Dong <ruijing.dong at amd.com>

Thanks,
Ruijing

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of boyuan.zhang at amd.com
Sent: Wednesday, July 10, 2024 4:30 PM
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Boyuan <Boyuan.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: [PATCH 2/2] drm/amdgpu/vcn: not pause dpg for unified queue

From: Boyuan Zhang <boyuan.zhang at amd.com>

For unified queue, DPG pause for encoding is done inside VCN firmware, so there is no need to pause dpg based on ring type in kernel.

For previous generations, pausing DPG for encoding in kernel is still needed.

v2: add more comments

Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f59e81be885d..00f3ac5f4572 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -412,7 +412,9 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
                for (i = 0; i < adev->vcn.num_enc_rings; ++i)
                        fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);

-               if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
+               /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
+               if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
+                   !adev->vcn.using_unified_queue) {
                        struct dpg_pause_state new_state;

                        if (fence[j] ||
@@ -458,7 +460,9 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
               AMD_PG_STATE_UNGATE);

-       if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
+       /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
+       if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
+           !adev->vcn.using_unified_queue) {
                struct dpg_pause_state new_state;

                if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { @@ -484,8 +488,12 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)

 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)  {
+       struct amdgpu_device *adev = ring->adev;
+
+       /* Only set DPG pause for VCN3 or below, VCN4 and above will be
+handled by FW */
        if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
-               ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
+           ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC &&
+           !adev->vcn.using_unified_queue)
                atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);

        atomic_dec(&ring->adev->vcn.total_submission_cnt);
--
2.34.1