[PATCH 5/6] drm/amdgpu: cache mclk/sclk min/max values
Pierre-Eric Pelloux-Prayer
pierre-eric.pelloux-prayer at amd.com
Tue Jun 18 15:23:26 UTC 2024
This way these values can be returned directly when using
AMDGPU_INFO_DEV_INFO, without waking up the GPU.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ++++++++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++++----
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 19 +++++--------------
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 8 ++++----
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 12 ++++++------
7 files changed, 40 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 083f353cff6e..75db8eba73d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -418,8 +418,16 @@ struct amdgpu_clock {
struct amdgpu_pll spll;
struct amdgpu_pll mpll;
/* 10 Khz units */
- uint32_t default_mclk;
- uint32_t default_sclk;
+ struct {
+ uint32_t min;
+ uint32_t max;
+ uint32_t def;
+ } mclk;
+ struct {
+ uint32_t min;
+ uint32_t max;
+ uint32_t def;
+ } sclk;
uint32_t default_dispclk;
uint32_t current_dispclk;
uint32_t dp_extclk;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 7dc102f0bc1d..f2c2b05233f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -658,9 +658,9 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
mpll->pll_in_max =
le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
- adev->clock.default_sclk =
+ adev->clock.sclk.def = adev->clock.sclk.min = adev->clock.sclk.max =
le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
- adev->clock.default_mclk =
+ adev->clock.mclk.def = adev->clock.mclk.min = adev->clock.mclk.max =
le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
mpll->min_post_div = 1;
@@ -699,8 +699,8 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
ret = 0;
}
- adev->pm.current_sclk = adev->clock.default_sclk;
- adev->pm.current_mclk = adev->clock.default_mclk;
+ adev->pm.current_sclk = adev->clock.sclk.def;
+ adev->pm.current_mclk = adev->clock.mclk.def;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index f932bec6e534..6eb125b1bd08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -719,13 +719,13 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
(union firmware_info *)(mode_info->atom_context->bios +
data_offset);
- adev->clock.default_sclk =
+ adev->clock.sclk.def = adev->clock.sclk.min = adev->clock.sclk.max =
le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
- adev->clock.default_mclk =
+ adev->clock.mclk.def = adev->clock.mclk.min = adev->clock.mclk.max =
le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
- adev->pm.current_sclk = adev->clock.default_sclk;
- adev->pm.current_mclk = adev->clock.default_mclk;
+ adev->pm.current_sclk = adev->clock.sclk.def;
+ adev->pm.current_mclk = adev->clock.mclk.def;
ret = 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3fb02f5b91c9..03417e7e8961 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4422,6 +4422,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_device_check_iommu_direct_map(adev);
+ if (adev->pm.dpm_enabled) {
+ adev->clock.sclk.min = amdgpu_dpm_get_sclk(adev, true);
+ adev->clock.sclk.max = amdgpu_dpm_get_sclk(adev, false);
+ adev->clock.mclk.min = amdgpu_dpm_get_mclk(adev, true);
+ adev->clock.mclk.max = amdgpu_dpm_get_mclk(adev, false);
+ }
+
return 0;
release_ras_con:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index dbb05d51682b..781851cf8dc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -827,19 +827,10 @@ static int amdgpu_info(struct drm_device *dev, void *data, struct drm_file *filp
dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
/* return all clocks in KHz */
dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
- if (adev->pm.dpm_enabled) {
- dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
- dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
- dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
- dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
- } else {
- dev_info->max_engine_clock =
- dev_info->min_engine_clock =
- adev->clock.default_sclk * 10;
- dev_info->max_memory_clock =
- dev_info->min_memory_clock =
- adev->clock.default_mclk * 10;
- }
+ dev_info->min_engine_clock = adev->clock.sclk.min * 10;
+ dev_info->max_engine_clock = adev->clock.sclk.max * 10;
+ dev_info->min_memory_clock = adev->clock.mclk.min * 10;
+ dev_info->max_memory_clock = adev->clock.mclk.max * 10;
dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
adev->gfx.config.max_shader_engines;
@@ -1315,12 +1306,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case AMDGPU_INFO_MAX_IBS:
case AMDGPU_INFO_GPUVM_FAULT:
case AMDGPU_INFO_GB_ADDR_CONFIG:
+ case AMDGPU_INFO_DEV_INFO:
need_runtime_pm = false;
break;
case AMDGPU_INFO_TIMESTAMP:
case AMDGPU_INFO_READ_MMR_REG:
- case AMDGPU_INFO_DEV_INFO:
case AMDGPU_INFO_SENSOR:
need_runtime_pm = true;
break;
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 6bb42d04b247..75c262acb704 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -2996,10 +2996,10 @@ static int kv_dpm_sw_init(void *handle)
adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
- adev->pm.default_sclk = adev->clock.default_sclk;
- adev->pm.default_mclk = adev->clock.default_mclk;
- adev->pm.current_sclk = adev->clock.default_sclk;
- adev->pm.current_mclk = adev->clock.default_mclk;
+ adev->pm.default_sclk = adev->clock.sclk.def;
+ adev->pm.default_mclk = adev->clock.mclk.def;
+ adev->pm.current_sclk = adev->clock.sclk.def;
+ adev->pm.current_mclk = adev->clock.mclk.def;
adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
if (amdgpu_dpm == 0)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index a1baa13ab2c2..e72eb59af6a5 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7232,8 +7232,8 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
u16 vddc, vddci, mvdd;
amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
- pl->mclk = adev->clock.default_mclk;
- pl->sclk = adev->clock.default_sclk;
+ pl->mclk = adev->clock.mclk.def;
+ pl->sclk = adev->clock.sclk.def;
pl->vddc = vddc;
pl->vddci = vddci;
si_pi->mvdd_bootup_value = mvdd;
@@ -7733,10 +7733,10 @@ static int si_dpm_sw_init(void *handle)
adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
- adev->pm.default_sclk = adev->clock.default_sclk;
- adev->pm.default_mclk = adev->clock.default_mclk;
- adev->pm.current_sclk = adev->clock.default_sclk;
- adev->pm.current_mclk = adev->clock.default_mclk;
+ adev->pm.default_sclk = adev->clock.sclk.def;
+ adev->pm.default_mclk = adev->clock.mclk.def;
+ adev->pm.current_sclk = adev->clock.sclk.def;
+ adev->pm.current_mclk = adev->clock.mclk.def;
adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
if (amdgpu_dpm == 0)
--
2.40.1
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