[PATCH] drm/amdgpu/jpeg5: reprogram doorbell setting after power up for each playback

Feng, Kenneth Kenneth.Feng at amd.com
Wed Jun 19 05:49:24 UTC 2024


[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Kenneth Feng <kenneth.feng at amd.com>


-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Sonny Jiang
Sent: Wednesday, June 19, 2024 12:40 AM
To: amd-gfx at lists.freedesktop.org
Cc: Jiang, Sonny <Sonny.Jiang at amd.com>
Subject: [PATCH] drm/amdgpu/jpeg5: reprogram doorbell setting after power up for each playback

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From: Sonny Jiang <sonjiang at amd.com>

Doorbell needs to be configured after power up during each playback

Signed-off-by: Sonny Jiang <sonjiang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 68ef29bc70e2..e766b9463759 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -137,10 +137,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
        adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
                        (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);

-       WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
-                       ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
-                       VCN_JPEG_DB_CTRL__EN_MASK);
-
        r = amdgpu_ring_test_helper(ring);
        if (r)
                return r;
@@ -314,6 +310,10 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
                JPEG_SYS_INT_EN__DJRBC0_MASK,
                ~JPEG_SYS_INT_EN__DJRBC0_MASK);

+       WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
+               ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
+               VCN_JPEG_DB_CTRL__EN_MASK);
+
        WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
        WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
        WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
--
2.45.1



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