[PATCH] drm/amdgpu: part I - normalize registers as local xcc to read/write under sriov in TLB

[Jian, Jane]

[AMD Official Use Only - AMD Internal Distribution Only]

+ mark
Hi Lijo @Lazar, Lijo,
Please help review this part I patch.
For sriov read/write part, we find a bug while masking the offset, which needs time to debug and later I will submit patch II.

Thanks,
Jane
-----Original Message-----
From: Jane Jian <Jane.Jian at amd.com>
Sent: Wednesday, June 19, 2024 5:55 PM
To: Lazar, Lijo <Lijo.Lazar at amd.com>; Chang, HaiJun <HaiJun.Chang at amd.com>; Zhao, Victor <Victor.Zhao at amd.com>
Cc: amd-gfx at lists.freedesktop.org; Jian, Jane <Jane.Jian at amd.com>
Subject: [PATCH] drm/amdgpu: part I - normalize registers as local xcc to read/write under sriov in TLB

[WHY]
sriov has the higher bit violation when flushing tlb

[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd

[TODO]
later will add the normalization in sriovw/rreg after fixing bugs

Signed-off-by: Jane Jian <Jane.Jian at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 ++
 drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c |  9 +++++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      | 10 ++++++++--
 drivers/gpu/drm/amd/amdgpu/soc15.c         |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.h         |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15_common.h  |  3 +++
 6 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 083f353cff6e..da8d3669cc23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -632,6 +632,8 @@ struct amdgpu_asic_funcs {
                                  const struct amdgpu_video_codecs **codecs);
        /* encode "> 32bits" smn addressing */
        u64 (*encode_ext_smn_addressing)(int ext_id);
+       /* normalize offset to keep in lower 16-bit */
+       u32 (*normalize_xcc_reg_offset)(u32 offset);

        ssize_t (*get_reg_state)(struct amdgpu_device *adev,
                                 enum amdgpu_reg_state reg_state, void *buf, diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 2c9a0aa41e2d..3306df74457b 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -1085,3 +1085,12 @@ ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,

        return size;
 }
+
+u32 aqua_vanjaram_normalize_xcc_reg_offset(u32 offset) {
+       u32 normalized_offset;
+
+       normalized_offset = offset & 0xffff;
+
+       return normalized_offset;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 88b4644f8e96..fba2e4ad58db 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -853,8 +853,14 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
         */
        if (adev->gfx.kiq[inst].ring.sched.ready &&
            (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
-               uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
-               uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
+
+               /* Select lower 16 bits to write in local xcc
+                * for MMHUB it uses xcc0, NO cross AID reg offset
+                */
+               if (AMDGPU_IS_GFXHUB(vmhub)) {
+                       req = NORMALIZE_XCC_REG_OFFSET(req);
+                       ack = NORMALIZE_XCC_REG_OFFSET(ack);
+               }

                amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
                                                 1 << vmid, inst);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8d16dacdc172..31037f068902 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -927,6 +927,7 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
        .query_video_codecs = &soc15_query_video_codecs,
        .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
        .get_reg_state = &aqua_vanjaram_get_reg_state,
+       .normalize_xcc_reg_offset = &aqua_vanjaram_normalize_xcc_reg_offset,
 };

 static int soc15_common_early_init(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 282584a48be0..0d405a474283 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -124,4 +124,5 @@ ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,  void vega10_doorbell_index_init(struct amdgpu_device *adev);  void vega20_doorbell_index_init(struct amdgpu_device *adev);  void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
+u32 aqua_vanjaram_normalize_xcc_reg_offset(u32 offset);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 242b24f73c17..43887836377d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -210,4 +210,7 @@
 #define WREG64_MCA(ext, mca_base, idx, val) \
        WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val)

+#define NORMALIZE_XCC_REG_OFFSET(offset) \
+       (amdgpu_sriov_vf(adev) ? \
+       adev->asic_funcs->normalize_xcc_reg_offset(offset) : offset)
 #endif
--
2.34.1