[PATCH] drm/amdgpu: clear IH_RB_W/RPTR during enabling interrupts in sriov case

[Christian König]

Am 20.06.24 um 15:55 schrieb Danijel Slivka:
> Clearing the IH_RB_W/RPTR during interrupts disable is not clearing
> the RB_OVERFLOW bit.
> Adding workaround to clear the wptr when enabling interrupts in case
> RB_OVERFLOW bit is set.
>
> Signed-off-by: Danijel Slivka <danijel.slivka at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 3cb64c8f7175..d6212a98ca99 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -147,6 +147,12 @@ static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev,
>   	}
>   
>   	if (enable) {
> +		if (amdgpu_sriov_vf(adev) &&
> +		    REG_GET_FIELD(RREG32(ih_regs->ih_rb_wptr), IH_RB_WPTR, RB_OVERFLOW)) {
> +			/* clear rptr, wptr*/
> +			WREG32(ih_regs->ih_rb_rptr, 0);
> +			WREG32(ih_regs->ih_rb_wptr, 0);
> +		}

Well that change doesn't really make much sense. We disable the IH ring 
before we do any initialisation, see ih_v6_0_irq_init().

That in turn sets RPTR and WPTR to 0:

                 /* set rptr, wptr to 0 */
                 WREG32(ih_regs->ih_rb_rptr, 0);
                 WREG32(ih_regs->ih_rb_wptr, 0);
                 ih->enabled = false;

So why should this be needed here?

Regards,
Christian.

>   		ih->enabled = true;
>   	} else {
>   		/* set rptr, wptr to 0 */