[PATCH] drm/amdgpu/gfx10: handle SDMA in KIQ map/unmap
Alex Deucher
alexander.deucher at amd.com
Thu Jun 20 17:29:11 UTC 2024
Add support for SMDA to the KIQ map/unmap functions.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 85 +++++++++++++++++++++-----
drivers/gpu/drm/amd/amdgpu/nvd.h | 2 +
2 files changed, 73 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18488c02d1cf..abbf906496fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3693,25 +3693,58 @@ static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
{
uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
uint64_t wptr_addr = ring->wptr_gpu_addr;
- uint32_t eng_sel = 0;
+ uint32_t eng_sel, ext_eng_sel;
- switch (ring->funcs->type) {
- case AMDGPU_RING_TYPE_COMPUTE:
- eng_sel = 0;
- break;
- case AMDGPU_RING_TYPE_GFX:
- eng_sel = 4;
- break;
- case AMDGPU_RING_TYPE_MES:
- eng_sel = 5;
- break;
- default:
- WARN_ON(1);
+ if (amdgpu_ip_version(kiq_ring->adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0)) {
+ ext_eng_sel = 0;
+ switch (ring->funcs->type) {
+ case AMDGPU_RING_TYPE_COMPUTE:
+ eng_sel = 0;
+ break;
+ case AMDGPU_RING_TYPE_GFX:
+ eng_sel = 4;
+ break;
+ case AMDGPU_RING_TYPE_MES:
+ eng_sel = 5;
+ break;
+ case AMDGPU_RING_TYPE_SDMA:
+ eng_sel = 2 + ring->me;
+ break;
+ default:
+ eng_sel = 0;
+ WARN_ON(1);
+ break;
+ }
+ } else {
+ switch (ring->funcs->type) {
+ case AMDGPU_RING_TYPE_COMPUTE:
+ ext_eng_sel = 0;
+ eng_sel = 0;
+ break;
+ case AMDGPU_RING_TYPE_GFX:
+ ext_eng_sel = 0;
+ eng_sel = 4;
+ break;
+ case AMDGPU_RING_TYPE_MES:
+ ext_eng_sel = 0;
+ eng_sel = 5;
+ break;
+ case AMDGPU_RING_TYPE_SDMA:
+ ext_eng_sel = 1;
+ eng_sel = ring->me;
+ break;
+ default:
+ eng_sel = 0;
+ ext_eng_sel = 0;
+ WARN_ON(1);
+ break;
+ }
}
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+ PACKET3_MAP_QUEUES_EXTENDED_ENGINE_SEL(ext_eng_sel) |
PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
@@ -3733,11 +3766,35 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
enum amdgpu_unmap_queues_action action,
u64 gpu_addr, u64 seq)
{
- uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
+ uint32_t eng_sel, ext_eng_sel;
+
+ if (amdgpu_ip_version(kiq_ring->adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0)) {
+ ext_eng_sel = 0;
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX)
+ eng_sel = 4;
+ else if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
+ eng_sel = 0;
+ else
+ /* SDMA */
+ eng_sel = 2 + ring->me;
+ } else {
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+ ext_eng_sel = 0;
+ eng_sel = 4;
+ } else if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ ext_eng_sel = 0;
+ eng_sel = 0;
+ } else {
+ /* SDMA */
+ ext_eng_sel = 1;
+ eng_sel = ring->me;
+ }
+ }
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
PACKET3_UNMAP_QUEUES_ACTION(action) |
+ PACKET3_UNMAP_QUEUES_EXTENDED_ENGINE_SEL(ext_eng_sel) |
PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h
index 631dafb92299..e0fd205cdd3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
@@ -400,6 +400,7 @@
* 7. WPTR_ADDR_HI [31:0]
*/
/* CONTROL */
+# define PACKET3_MAP_QUEUES_EXTENDED_ENGINE_SEL(x) ((x) << 2)
# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
@@ -427,6 +428,7 @@
* 2 - DISABLE_PROCESS_QUEUES
* 3 - PREEMPT_QUEUES_NO_UNMAP
*/
+# define PACKET3_UNMAP_QUEUES_EXTENDED_ENGINE_SEL(x) ((x) << 2)
# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
--
2.45.2
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