[PATCH 2/2] drm/amdgpu: Use offsets local to VCN in VF

[Christian König]

Am 05.03.24 um 10:03 schrieb Lazar, Lijo:
>
> On 3/5/2024 2:24 PM, Christian König wrote:
>>
>> Am 05.03.24 um 07:40 schrieb Lijo Lazar:
>>> For VCN 4.0.3, use only the local addressing scheme while in VF
>>> mode. This includes addressing scheme used for HUB offsets.
>>>
>>> Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 20 +++++++++++++++++++-
>>>    1 file changed, 19 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> index 7b5ad13b618e..a27f3f260aab 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> @@ -1381,6 +1381,24 @@ static uint64_t
>>> vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)
>>>                        regUVD_RB_WPTR);
>>>    }
>>>    +static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring
>>> *ring,
>>> +                unsigned int vmid, uint64_t pd_addr)
>>> +{
>>> +    struct amdgpu_vmhub *hub;
>>> +
>>> +    /* For VF, only local offsets should be used */
>>> +    if (amdgpu_sriov_vf(ring->adev))
>>> +        ring->vm_hub = AMDGPU_MMHUB0(0);
>> That is clearly a no-go since the vm_hub must be statically and can't be
>> changed here.
>>
> After HUB allocation, the only usage of this hub pointer is to calculate
> use the right offset. We still want VCN to use the right hub, only thing
> is register offsets in MMHUB(0) are equal to 'local offsets'.

The vm_hub is a static setup describing how the engine works. You 
basically just insert an illegal value here to fix your register offset 
calculation.

That is absolutely *not* something you can do.

What exactly is the requirement?

Regards,
Christian.

>
> Thanks,
> Lijo
>
>> Regards,
>> Christian.
>>
>>> +    hub = &ring->adev->vmhub[ring->vm_hub];
>>> +
>>> +    pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
>>> +
>>> +    /* wait for reg writes */
>>> +    vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
>>> +                    vmid * hub->ctx_addr_distance,
>>> +                    lower_32_bits(pd_addr), 0xffffffff);
>>> +}
>>> +
>>>    static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>>>    {
>>>        /* VCN engine access for HDP flush doesn't work when RRMT is
>>> enabled.
>>> @@ -1443,7 +1461,7 @@ static const struct amdgpu_ring_funcs
>>> vcn_v4_0_3_unified_ring_vm_funcs = {
>>>        .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
>>>        .emit_ib = vcn_v2_0_enc_ring_emit_ib,
>>>        .emit_fence = vcn_v2_0_enc_ring_emit_fence,
>>> -    .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
>>> +    .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,
>>>        .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,
>>>        .test_ring = amdgpu_vcn_enc_ring_test_ring,
>>>        .test_ib = amdgpu_vcn_unified_ring_test_ib,