[PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS

Zhang, Hawking Hawking.Zhang at amd.com
Mon Mar 11 02:55:56 UTC 2024


[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Zhou1, Tao
Sent: Monday, March 11, 2024 10:45
To: amd-gfx at lists.freedesktop.org
Subject: RE: [PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS

[AMD Official Use Only - General]

[AMD Official Use Only - General]

Ping for the series...

> -----Original Message-----
> From: Zhou1, Tao <Tao.Zhou1 at amd.com>
> Sent: Friday, February 23, 2024 4:24 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>
> Subject: [PATCH 1/5] drm/amdgpu: add new bit definitions for GC 9.0
> PROTECTION_FAULT_STATUS
>
> Add UCE and FED bit definitions.
>
> Signed-off-by: Tao Zhou <tao.zhou1 at amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> index efc16ddf274a..2dfa0e5b1aa3 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> @@ -6822,6 +6822,8 @@
>  #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
> 0x14
>  #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
> 0x18
>  #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
> 0x19
> +#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT
> 0x1d
> +#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT
> 0x1e
>  #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
> 0x00000001L
>  #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
> 0x0000000EL
>  #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
> 0x000000F0L
> @@ -6832,6 +6834,8 @@
>  #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
> 0x00F00000L
>  #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK
> 0x01000000L
>  #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
> 0x1E000000L
> +#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK
> 0x20000000L
> +#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK
> 0x40000000L
>  //VM_L2_PROTECTION_FAULT_ADDR_LO32
>  #define
> VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIF
> T                                       0x0
>  #define
> VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
> 0xFFFFFFFFL
> --
> 2.34.1



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